Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2

Johnson, F.S.; Miles, D.; Grider, D. T.; Wortman, J. J.

doi:10.1007/bf02665519

Cited by 55 publications

(13 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, low temperature selective epitaxy might be well suited. 23,24) In Fig. 5 we show the simulated transfer characteristics for the p-channel operating mode.…”

Section: Sige Lateral Tunnel Fetmentioning

confidence: 99%

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Bhuwalka

Born

Schindler

et al. 2006

jjap

100

View full text Add to dashboard Cite

Experimental results of p-channel silicon vertical tunnel field-effect transistors down to sub-50 nm channel length are shown. As predicted by two-dimensional simulations, we show that the device on-current is nearly independent of channel length scaling. As the drain current is determined by electrons tunneling from the valence band to the conduction band, we show that mobility does not play any role in determining the device characteristics. Low temperature measurements reveal weak positive temperature coefficient in the transfer characteristics due to the dependence of bandgap on temperature. However, as expected for the silicon devices, low on-current is observed. Thus, we propose a lateral tunnel FET on SiGe-on-insulator with high oncurrents and symmetric performance in n-channel as well as p-channel operating modes.

show abstract

“…However, low temperature selective epitaxy might be well suited. 23,24) In Fig. 5 we show the simulated transfer characteristics for the p-channel operating mode.…”

Section: Sige Lateral Tunnel Fetmentioning

confidence: 99%

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Bhuwalka

Born

Schindler

et al. 2006

jjap

100

View full text Add to dashboard Cite

show abstract

“…2 shows that the spacer technique provides very low CD variation compared to e-beam lithography with SAL-601 resist. Sacrificial Si 0:4 Ge 0:6 was removed with (5:1:1) [11]. HTO, thermally grown oxide, nitride, and silicon were not etched significantly in this solution.…”

Section: Device Fabricationmentioning

confidence: 99%

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

Choi

King

2002

Solid-State Electronics

View full text Add to dashboard Cite

“…Reaction between radicals and exposed surface yields volatile materials and continues further reaction. [38], [39]. With this mechanism, SiGe can be successfully removed with selectivity of 20:1 to Si ( Fig.…”

Section: Fin Patterningmentioning

confidence: 98%

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Seo

Kim

Lee

et al. 2019

2019 Electron Devices Technology and Manufacturing Conference (EDTM)

View full text Add to dashboard Cite

Exploding demands for mobile devices induce the drastic expansion of the market of NAND flash memory as high density storage devices. Threedimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension. For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) will be a roadblock in scaling-down of the minimum feature size, while channel diameter can be scaled down to < 20 nm. It is challenging to reduce the thickness of oxide-nitride-oxide (ONO) layer, since the charge trapping properties degrade when the Si3N4 is made thinner..In this thesis, the channel stacked NAND flash memory array (CSTAR) with high-κ charge trapping layer for high scalability is proposed. To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices. Finally, 4-layer channel stacked memory with high-κ layer was successfully fabricated and ii characterized.Recent trend of nonvolatile memories are introduced and the overview of 3D stacked NAND flash memory technology is presented in Chapter 1 and 2.In Chapter 3, the memory characteristics of high-κ layer were evaluated with fabricated capacitors and flash memory devices. In Chapter 4, fabrication process and electrical characteristics of CSTAR with high-κ are shown. With the comparison with previous works using ONO layer, CSTAR with high-κ is evaluated. In Chapter 5, the novel operation method of CSTAR is presented.Using TCAD and measurement, a newly designed operation method is verified.

show abstract

Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2

Cited by 55 publications

References 12 publications

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Contact Info

Product

Resources

About