The scanning capacitance microscope ͑SCM͒ is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope ͑SPM͒. As reported in Edwards et al. ͓Appl. Phys. Lett. 72, 698 ͑1998͔͒, scanning capacitance spectroscopy ͑SCS͒ is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.

In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm 2 , and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm 2 ) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.

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Rapid thermal processing (RTP) has been considered from a manufacturing point of view as a potential technology for depositing thin films by low-pressure chemical vapor deposition (LPCVD) in a single wafer manufacturing environment in this work. The results of this study suggest that new chemical processes must be developed to satisfy the throughput requirements of single wafer manufacturing and the demands of cold-wall reactor design. Issues such as temperature measurement and uniformity are reviewed and reconsidered in the context of LPCVD. New tool requirements for reduced pressure operation are discussed. New advances in tool design are needed (especially in temperature measurement) before rapid thermal chemical vapor deposition (RTCVD) can be considered as a routine manufacturable process.