Selective Fault Tolerance for Register Files of Graphics Processing Units

Goncalves, Marcio M.; Fernandes, Fernando; Lamb, Ivan Peter; Rech, Paolo; Azambuja, Jose Rodrigo

doi:10.1109/tns.2019.2903027

Cited by 9 publications

(6 citation statements)

References 19 publications

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“…Recent works that study the vulnerability in the presence of soft errors in various accelerators are reviewed in [4]. These works are based on either neutron beam experiments on real platforms [7], [11], or fault injections using either highlevel simulation [12]- [14], or emulation [15]- [19]. This paper extends our previous work in [18], [19], an emulation-based fault injection framework, to provide fine-grain vulnerability analysis of a resource constrained edge accelerator architecture.…”

Section: Introductionmentioning

confidence: 93%

“…Existing redundancy techniques for soft error mitigation come with high cost on area, power, and performance, which edge devices cannot afford [6]. Consequently, it is important to explore the vulnerability of these devices at design time and apply selective redundancy at a fine-grained level, as needed [7]- [10]. Recent works that study the vulnerability in the presence of soft errors in various accelerators are reviewed in [4].…”

Section: Introductionmentioning

confidence: 99%

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Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Corneliou

Nikolaou

Michael

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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The use of Neural Network (NN) inference on edge devices necessitates the development of customized Neural Inference Accelerators (NIA) in an attempt to meet performance and accuracy requirements. However, edge infrastructure often relies on highly constrained resources with limited power budget and area footprint. At the same time, reliability is very crucial, especially, for critical applications and trade-offs area and power due to the needed for protection. In this paper, we study the soft-error vulnerability of an edge NIA, using an emulationbased fault injection framework, which allows for accurate and fine-grained analysis. We consider the tinyTPU architecture, which resembles Google's Tensor Processing Unit (TPU) but is optimized for edge-based applications. Through a proposed error outcome taxonomy for NN-based algorithms, we study the criticality of each NIA component and explore their vulnerability to Single Event Upsets (SEU), while providing analysis of performance-accuracy trade-offs such as using smaller NN models and periodic memory refresh. Further, through analysis of the tinyTPU architecture, we manage to considerably reduce the emulation time for components with non-persistent faults.

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Section: Introductionmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Corneliou

Nikolaou

Michael

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

show abstract

“…However, some components can be inherently tolerant to errors, and thus, may not require protection [42]. Therefore, selective hardware redundancybased protection can significantly reduce area and power overheads with minimal impact on system's reliability [15], [16], [35], [42]. To avoid costly and unnecessary use of redundancy mechanisms, the reliability of individual components, along with the quality of the application's output, must be accurately assessed first.…”

Section: Related Workmentioning

confidence: 99%

Functional and Timing Implications of Transient Faults in Critical Systems

Kritikakou

Nikolaou

Rodriguez-Ferrandez

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Embedded systems in critical domains, such as automotive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.

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“…This approach can detect all errors at the performance cost of increasing execution time up to 150% [9,10]. Partial hardening can decrease this performance cost in exchange for less fault coverage by selectively duplicating instructions and registers based on their criticalities [11,12].…”

Section: Related Workmentioning

confidence: 99%

Improving GPU register file reliability with a comprehensive ISA extension

Goncalves

Condia

Reorda

et al. 2020

Microelectronics Reliability

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This work proposes a comprehensive ISA extension to improve GPU reliability to transient effects. Three additional instructions are proposed, implemented, and combined with software-based datapath duplication. Modified program codes are compared to state-of-the-art software-based fault tolerance techniques in terms of execution time. The circuit area is evaluated against the original GPU architecture, and a fault injection campaign is performed to assess reliability. Results show that this comprehensive ISA extension improves performance and fault detection capabilities of software-based approaches at negligible costs in terms of circuit area. This work can help engineers in designing more efficient and resilient GPU architectures.

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Selective Fault Tolerance for Register Files of Graphics Processing Units

Cited by 9 publications

References 19 publications

Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Functional and Timing Implications of Transient Faults in Critical Systems

Improving GPU register file reliability with a comprehensive ISA extension

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