Selective State Retention Power Gating Based on Formal Verification

Greenberg, Shlomo; Rabinowicz, Joseph; Manor, Erez

doi:10.1109/tcsi.2014.2373031

Cited by 7 publications

(7 citation statements)

References 17 publications

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“…However, this method requires a formal representation of the entire design, which is not always available, and also no automated techniques are proposed. The two recently published SSRPG approaches introduced by [16,17] provide pure formal methods for automatic selecting of all the FF's, which require retention and are essential for a proper system recovery upon power-up. Experimental results show a significant reduction of about 80% of the retention cells area overhead.…”

Section: Introductionmentioning

confidence: 99%

“…Recent SSRPG techniques can be efficiently applied to new modern SoC designs for automatic selection and formal validation of essential FFs requires retention. The current work is based on our previous formal SSRPG approach presented in [17], which utilizes formal verification methods and therefore can be easily implemented using the new proposed physical design flow.…”

Section: Introductionmentioning

confidence: 99%

“…Although some previous research works [16,17] try to estimate the area and powersaving factor results from applying the SRPG selective approaches, none of them validate it on real physical design implementation. Hence, one of the main objectives of this work is to quantify the real area and power saving factors while using SSRPG comparing to SRPG.…”

Section: Introductionmentioning

confidence: 99%

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A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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“…Greenberg et al recently proposed methods [9,10] for automatically classifying all the flip-flops (FFs) of a given design into two categories: essential FF (e-FF) and redundant FF (r-FF). [10] performs the analysis according to read/write criteria on the synthesized gate-level netlist with Binary Decision Diagram (BDD) as the data structure, while [9] represented the criteria as a set of formal properties using propositional formulas and then uses common formal verification tools to drive the identification of the e-FFs. Even though the proposed approaches are formally sound, they are difficult to be applied by nonformal experts due to the required effort to provide proper input constraints using BDDs.…”

mentioning

confidence: 99%

“…In addition, They need massive parallel processing to achieve reasonable runtime, leaving scalability a major concern. Compared with [9,10], our proposed method verifies power intention and retention scheme in the early phase of design flow by symbolic simulation [4,5], which allows us to handle not only gate-level but also RTL designs without logic synthesis. Performing the analysis at the RTL instead of gate-level makes it easier for the designer to inspect the results.…”

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confidence: 99%

Scalable sequence-constrained retention register minimization in power gating design

Chiang

Chang

Liu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Retention registers are utilized in power gating design to hold design state during power down and to allow safe and fast system reactivation. Since a retention register consumes more power and costs more area than a non-retention register, it is desirable to minimize the use of retention registers. However, relaxing retention requirement to a minimal subset of registers can be computationally challenging. In this paper, we adopt satisfiability solving for scalable selection of registers whose retention is unnecessary and exploit input sequence constraints to increase the number of non-retention registers. Empirical results on industrial benchmarks show that our proposed methods are efficient and effective in identifying non-retention registers.

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Reliable and ultra-low power approach for designing of logic circuits

Haq,

Sharma

2023

Analog Integr Circ Sig Process

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Selective State Retention Power Gating Based on Formal Verification

Cited by 7 publications

References 17 publications

A New Physical Design Flow for a Selective State Retention Based Approach

A New Physical Design Flow for a Selective State Retention Based Approach

Scalable sequence-constrained retention register minimization in power gating design

Reliable and ultra-low power approach for designing of logic circuits

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