2013 IEEE International Reliability Physics Symposium (IRPS) 2013
DOI: 10.1109/irps.2013.6532036
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Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Abstract: This paper describes various measurem performed on Intel's 22nm process technology reliability implications. Comparisons to thermal and analytical data show excellent matching.I.

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Cited by 70 publications
(17 citation statements)
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“…As discussed in Ref. [47], the channel temperature may be increased in tri-gate devices due to the reduced heat conduction to the substrate, as shown below in Fig.3 the channel temperature is known to depend on the size and layout of the transistors. As a result, the total channel temperature must be calculated as the combination of the ambient temperature plus a self-heat function of both power dissipation and transistor layout.…”
Section: Self-heat In Tri-gatementioning
confidence: 95%
See 1 more Smart Citation
“…As discussed in Ref. [47], the channel temperature may be increased in tri-gate devices due to the reduced heat conduction to the substrate, as shown below in Fig.3 the channel temperature is known to depend on the size and layout of the transistors. As a result, the total channel temperature must be calculated as the combination of the ambient temperature plus a self-heat function of both power dissipation and transistor layout.…”
Section: Self-heat In Tri-gatementioning
confidence: 95%
“…For example, the sidewall crystal orientation is generally chosen to be <110> to improve transistor performance [46], but can affect the interface quality. Additionally, top corners can enhance local electric fields [47] and the vertical sidewalls require special integration schemes to ensure appropriate gate [48] and junction formation. Perhaps most critically, the fin architecture limits heat dissipation from the channel, which can lead to increased local temperatures [49].…”
Section: The Tri-gate Influences On Agingmentioning
confidence: 99%
“…It is therefore necessary to develop a SPICE compatible compact model to evaluate parametric drift due to HCD for the full VG-VD stress condition, including VG <, = and > VD. If present, BTI [5], [6], SH [7] and HCD-BTI coupling [8] in the presence of SH can further complicate the modeling efforts.…”
Section: Introductionmentioning
confidence: 99%
“…The heat conduction property is one of the main concerns for nanoscale FETs relating to reliability and performance [1] [2]. The non-planar structures surrounded by insulating films are preferred to maintain the gate controllability.…”
Section: Introductionmentioning
confidence: 99%