Self-Heating and Electrothermal Properties of Advanced Sub-5-nm Node Nanoplate FET

Myeong, Ilho; Song, Ickhyun; Kang, Min Jae; Shin, Hyungcheol

doi:10.1109/led.2020.2998460

Cited by 35 publications

(11 citation statements)

References 19 publications

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“…Furthermore, thermal conductivity degradation due to phonon boundary scattering in doped silicon layers must be considered [29]. As presented in Table I, accurate thermal conductivity values of the device regions with respect to dimension and doping concentration were applied to the simulation [28], [30].…”

Section: Design and Simulation Methodologymentioning

confidence: 99%

“…The AC transient characteristics of the CFET in 3D mixedmode CMOS inverter simulations [32], [39] were examined in terms of the vertical separation distance between the top NFET and bottom PFET devices (DN/P), which is known to greatly impact the AC and thermal performance of multistacked transistors [3], [28]. The DN/P variation range was decided to be 10 to 30 nm, based on the industry-relevant replacement metal gate (RMG) process used for stacked nanosheet FETs and CFETs [3], [4], [40], [41], and was varied in 5 splits similarly to the method used by [28]. Fig.…”

Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

“…5(c). The smaller separation distance leads to reduced device capacitance due to less gate-S/D overlap area [28] and mitigated gate fringing effects [4], which are the largest components of parasitic capacitance in a multi-gate CMOS logic circuit [41]- [43]. It is also observed that as DN/P is reduced, the slope of Ceff decreases as the capacitive coupling between the top and bottom device increases with closer distance.…”

Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

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Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5% and the RC delay up to 9.6%, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9% faster operation frequency and 3.4% reduced dynamic power loss, but 11.2% higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.INDEX TERMS Complementary FET (CFET), self-heating effect (SHE), 3D monolithic integration, TCAD, thermal resistance, time delay, figure of merit (FoM), CMOS inverter, device optimization.

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Section: Design and Simulation Methodologymentioning

confidence: 99%

Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

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Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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“…Such a channel created in the lower substrate results in a high risk of leakage current in the 3 nm dimension. Ideas discussed to date to reduce such substrate leakage include: (i) inserting an insulating oxide layer for bottom isolation, which is referred to here as then bottom oxide (BO) scheme [4,5] and (ii) doping the bottom substrate, which is referred to as the punch-through-stopper (PTS) doping scheme [6,7]. While the PTS doping scheme and the bottom oxide (BO) scheme can be studied separately, there has been no analysis of simultaneous optimization to date.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

et al. 2022

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In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.

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“…Это достигается за счет того, что затвор в FinFET блокирует утечку заряда через канал, пока транзистор находится в выключенном состоянии. Вместе с тем FinFET в рабочем режиме оперирует с током гораздо большей плотности, чем планарные устройства, что в свою очередь может приводить к существенному локальному нагреву такой структуры [7]. Помимо этого, большой ток может вызвать падение напряжения в сетках питания, в результате чего могут возникнуть сбои в работе вычислительных блоков.…”

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ИСПОЛЬЗОВАНИЕ ВСТРОЕННЫХ PVT-СЕНСОРОВ ПРИ РАЗРАБОТКЕ ПРОЕКТОВ НА БАЗЕ СОВРЕМЕННЫХ FinFET-ТЕХНОЛОГИЙ

Белоусов¹

2021

Electronics: STB Russia

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Рассматриваются общие принципы реализации системы диагностики и контроля современных систем на кристалле на базе FinFET с применением датчиков и контроллеров физических параметров, интегрируемых на этапе проектирования будущих устройств, на основе аппаратных компонентов платформы SLM от Synopsys.

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Self-Heating and Electrothermal Properties of Advanced Sub-5-nm Node Nanoplate FET

Cited by 35 publications

References 19 publications

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

ИСПОЛЬЗОВАНИЕ ВСТРОЕННЫХ PVT-СЕНСОРОВ ПРИ РАЗРАБОТКЕ ПРОЕКТОВ НА БАЗЕ СОВРЕМЕННЫХ FinFET-ТЕХНОЛОГИЙ

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