Self-Reconfiguration on Spartan-III FPGAs with Compressed Partial Bitstreams via a Parallel Configuration Access Port (cPCAP) Core

Abstract

This paper presents an alternative approach for dynamic partial self-reconfiguration that enables a Field Programmable Gate Array (FPGA) to reconfigure itself at run-time partially through a parallel configuration access port (cPCAP) under the control of the stand alone cPCAP core within the FPGA instead of using an embedded processor. The cPCAP core with bitstream decompression module needs only 361 slices , which is approximately 18% of a Spartan-3S200 FPGA. The dynamic partial self-reconfiguration via cPCAP core works up to 50Mbyte/s. The compressed partial bitstream is stored in BlockRAM within the FPGA and decompressed via cPCAP core at the time of reconfiguration of the FPGA. This approach has been implemented on a pure Spartan-3 FPGA from Xilinx, but it can also be used for any other FPGA architectures, such as Virtex-II(Pro), etc.

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

“…Researches such as (Bayar & Yurdakul 2008) and (Paulsson et al 2007) focus on implementing softcore internal configuration cores on Xilinx FPGAs such as Spartan-3, that do not have the hardware internal reconfiguration cores, for effective implementation of PDR. Finally in (Koch et al 2006), this reconfigurable core is connected with Network-on-Chip based FPGAs.…”

Block RAM-based architecture for real-time reconfiguration using Xilinx® FPGAs

“…Reducing the size of the bitstream will thus also reduce the reconfiguration time. Even though compression techniques such as Lempel-Ziv-Welch (LZW), LempelZiv (LZ7) or custom algorithms [1,25] are capable of reducing the bitstream significantly [26], the bitstream has to be decompressed before being sent to the configuration memory. Depending on the decompression algorithm used, this could contribute significantly to the reconfiguration time.…”

Addiguration: Exploring configuration behavior of Spartan-3 devices

“…In low cost Spartan-3 devices such a port is not available. However [10] and [11] have introduced a virtual ICAP port for self-reconfiguration of Spartan-3 FPGAs.…”

“…[10], [11]), Spartan-3 FPGAs are somewhat difficult to use in partial dynamic reconfigurable systems. The reason for this drawback can be found in the structure of the configuration logic.…”