Self-Testing Analog Spiking Neuron Circuit

El-Sayed, Sarah A.; Camuñas-Mesa, Luis A.; Linares-Barranco, B.; Stratigopoulos, Haralampos-G.

doi:10.1109/smacd.2019.8795234

Cited by 9 publications

(7 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Section: Introductionmentioning

confidence: 99%

“…Fault injection experiments showing the vulnerability of SNNs to hardware-level faults have been presented in [6], [7], [11]. A built-in self-test strategy is proposed for a biologicallyinspired spiking neuron in [7]. To the best of our knowledge, this is the first paper proposing a generic network-level neuron fault tolerance strategy for SNNs.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Neuron Fault Tolerance in Spiking Neural Networks

Spyrou¹,

El-Sayed²,

Afacan³

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

View full text Add to dashboard Cite

The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a largescale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM's DVS128 gesture datasets.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Neuron Fault Tolerance in Spiking Neural Networks

Spyrou¹,

El-Sayed²,

Afacan³

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

View full text Add to dashboard Cite

show abstract

“…A similar condition is proposed in [23] where spike generation is disabled if the membrane voltage stays above the threshold for more than two clock cycles. A BIST technique for biological spiking neurons that checks for the appearance of all expected firing patterns is proposed in [37]. Inherent fault resilience of SNNs when trained with different algorithms is studied in [35], in addition to showing how to modify a training algorithm to improve fault tolerance.…”

Section: Prior Art On Testing Ai Hardware Acceleratorsmentioning

confidence: 99%

Compact Functional Testing for Neuromorphic Computing Circuits

El-Sayed

Spyrou

Camuñas-Mesa

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

We address the problem of testing Artificial Intelligence (AI) hardware accelerators implementing Spiking Neural Networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the inter-class spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassififed with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modelled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.

show abstract

“…The prior art on dependability analysis of SNNs is still at a very early stage. In [11], a functional Built-In Self-Test (BIST) is proposed for biologically-inspired spiking neurons. The idea is to test in one-shot with a specially crafted stimulus that the neuron is capable of producing all the expected firing patterns.…”

Section: Introductionmentioning

confidence: 99%

Reliability Analysis of a Spiking Neural Network Hardware Accelerator

Spyrou¹,

El-Sayed²,

Afacan³

et al. 2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

View full text Add to dashboard Cite

Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.

show abstract

Self-Testing Analog Spiking Neuron Circuit

Cited by 9 publications

References 23 publications

Neuron Fault Tolerance in Spiking Neural Networks

Neuron Fault Tolerance in Spiking Neural Networks

Compact Functional Testing for Neuromorphic Computing Circuits

Reliability Analysis of a Spiking Neural Network Hardware Accelerator

Contact Info

Product

Resources

About