Settling Time Optimization for Three-Stage CMOS Amplifier Topologies

Shamsi

2011 IEEE EUROCON - International Conference on Computer as a Tool

et al. 2011

This paper presents a new time-domain design procedure for three-stage amplifiers with reversed nested Miller compensation (RNMC). By utilizing this method, the values of the compensation capacitors are properly selected to achieve the best settling time. To demonstrate the effectiveness of the proposed method, a three-stage amplifier is designed and simulated in a 1V, 90nm CMOS technology. Simulation results show that by using this method, the settling time of the threestage amplifier is approximately halved in comparison with the conventional approaches.

“…The Figure-of-Merit (FOM defined in [10]) comparison of our amplifier with other amplifiers reported in [10], shows that this amplifier is a high performance amplifier.…”

Section: Simulation Resultsmentioning

confidence: 69%

Section: B Compensation Network Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Settling time optimization in three-stage amplifiers with reversed nested Miller compensation

Shamsi

2011 IEEE EUROCON - International Conference on Computer as a Tool

et al. 2011

“…The dynamic settling error (DSE) results [20,21,25] The dynamic settling error (DSE) results [20,21,25] …”

Section: The Role Of the Separation Factor In The Settling Timementioning

confidence: 99%

Robust design of CMOS amplifiers oriented to settling‐time specification

Giustolisi

Palumbo

2016

Circuit Theory & Apps

In this paper, we propose a new approach for the robust design of complementary metal-oxide-semiconductor amplifiers based on settling-time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling-time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two-stage amplifier and a three-stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright

Analog Integr Circ Sig Process

“…There are several publications considering the optimization of settling performance in the design of multistage OTAs [7][8][9][10][11][12][13][14]. These publications have been aimed to improve the linear settling time by its optimization using systematic design methodologies.…”

Section: Introductionmentioning

confidence: 99%

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

Golabi

Yavari

2015

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.