SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Mavis, D.G.; Eaton, P.H.

doi:10.1109/relphy.2007.369907

Cited by 96 publications

(46 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In silicon, an LET of 97 MeV-cm 2 /mg corresponds to a charge deposition of 1 pC/um [8]. Parameter t 1 and t 2 are usually assumed to have values of 10 ps and 100∼200 ps respectively [7]. In this paper, we take t 1 = 10 ps and t 2 = 150 ps.…”

Section: Simulation Resultsmentioning

confidence: 99%

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

Wang

Zhang

Chen

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiplebit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100 Mev-cm 2 /mg.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

Wang

Zhang

Chen

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…INTRODUCTION HE continuous scaling of microelectronic technology enables to keep on increasing system complexity and performance. However, this comes together with an increased vulnerability of ICs to radiation-induced faults [1,2,3]. Particularly, it has been proven that single event transients (SETs) affecting storage elements (latches and flip-flops) are by far the major cause of soft errors (SEs) affecting sequential circuits [4,5].…”

Section: Index Terms-static Latch; Robust Latch; Soft Error; Aging;mentioning

confidence: 99%

Impact of Aging Phenomena on Latches’ Robustness

Omaña

Rossi

Edara

et al. 2016

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk TNANO-00456-2015 1  Abstract-In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider Bias Temperature Instability (BTI) affecting both nMOS (positive BTI) and pMOS (negative BTI), which is considered the most critical aging mechanism threatening the reliability of ICs. Our analyses show that, as an IC ages, BTI increases significantly the susceptibility of both standard latches and low-cost robust latches, whose robustness is based on the increase in the critical charge of their most susceptible node(s). Instead, we will show that BTI minimally affects the soft error susceptibility of more costly robust latches that avoid the generation of soft errors by design. Consequently, our analysis highlights the fact that, in applications mandating the use of low-cost robust latches, designers will have to face the problem of their robustness degradation during IC lifetime. Therefore, for these applications, designers will have to develop proper low-cost solutions to guarantee the minimal required level of robustness during the whole IC lifetime.

show abstract

“…However, this growth comes together with a reduction in ICs power supply and, consequently, noise margins, thus increasing significantly their vulnerability to radiation induced errors [1,2,3]. Particularly, it is expected that single event transients (SETs) affecting combinational logic will soon become a concern.…”

Section: Introductionmentioning

confidence: 99%

“…If this occurs and the SET satisfies the sampling element set-up and hold-time constraints, it gets latched, thus giving rise to a SE [3,4,5]. Intensive research has been devoted to the accurate modeling of SETs [1,2,6,7], as well as to the development of approaches to tolerate them [1,8].…”

Section: Introductionmentioning

confidence: 99%

Impact of Bias Temperature Instability on Soft Error Susceptibility

Rossi

Omaña

Metra

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , TVLSI-00281-2013 1 Impact of Bias Temperature Instability on Soft Error SusceptibilityAbstract-In this paper we address the issue of analyzing the effects of aging mechanisms on ICs' soft error susceptibility. Particularly, we consider Bias Temperature Instability (BTI), namely Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors, that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the soft error susceptibility of the whole IC. We then propose a time dependent model for soft error susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the IC's lifetime.Index Terms-Aging, bias temperature instability, critical charge, soft error.

show abstract

SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Cited by 96 publications

References 11 publications

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

Impact of Aging Phenomena on Latches’ Robustness

Impact of Bias Temperature Instability on Soft Error Susceptibility

Contact Info

Product

Resources

About