SEU experiments on an Artificial Neural Network implemented by means of digital processors

Velazco, Raoul; Assoum, A.; Cheynet, P.; Olmos, M.; Ecoffet, R.

doi:10.1109/23.556882

Cited by 10 publications

(1 citation statement)

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“…Physical modular redundancy and data codes (namely, AN codes [8,9]) have been shown effective to achieve this goal at a limited circuit complexity increase. Experiments on SEU sensitivity of neural networks are presented in [10], and preliminary results about the SEU susceptibility of antifuse-based FPGA are reported in [11]. A preliminary design of a neuron with fault-detection capabilities is presented in [12], while the neural approach for event identification is discussed in [13].…”

Section: Introductionmentioning

confidence: 99%

Implementing a self-checking neural system for photon event identification by SRAM-based FPGAs

Alderighi

D'Angelo²,

Piuri³

et al.

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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The paper presents and evaluates the design and the implementation of a self-checking neural system for photon event identification in Intensified Charge-Coupled Devices detectors. The neural approach reveals more effective than classical algorithmic approaches thanks to its learning through example ability. Implementation is accomplished by SRAM-based FPGAs, which have generated increasing interest in the space community. The adoption of suitable on-line fault detection techniques is illustrated taking into account in specific way SEU induced faults. The techniques are based on AN coding, particularly 3N coding, which constitutes a reasonable trade-off between circuit complexity and computational delay. Estimations of circuit area overhead and fault coverage are reported.

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