SEU performance of TAG based flip-flops

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $\mu$m

“…Previous data from the test of a 0.5 m chip indicated that a 3-TAG flip-flop [3] as shown in Fig. 3 was effective in resisting SEUs.…”

“…If the SET pulse widthis longer then it will propagate through the TAG or guard-gate. Input gating circuits are not shown in these figures (see [3] for details), but since this circuit should suppress SETs originating inside or outside the storage cell, asynchronous clear is allowed and was used in these designs.…”

“…5) also tested previously [3], separately proposed as an enhancement to the dual interlocked cell (DICE) [6], and called by some as a bias coupled flip-flop [7]. The 4-TAG latch has two data inputs, and will change state only when these inputs agree.…”

“…However, dual redundancy has been used to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], the guard-gate [2], or a Transition AND Gate (TAG) [3]. A two input guard-gate or TAG is shown in Fig.…”

Redundancy Based on a Fault-Tolerant Gate Array Cell

“…The temporal flip-flop design proposed in this thesis will use a C-element configuration for the storage nodes in both the master and slave latches. Driving two C-element inputs with two other Celements has also been shown to provide an effective method to incorporate redundancy into temporal designs [21].…”