SEU Recovery Mechanism for SRAM-Based FPGAs

Abstract

The application of SRAM-based field-programmable gate arrays (FPGAs) in mission-critical systems requires errormitigation and recovery techniques to protect them from the errors caused by high-energy radiation, also known as single event upsets (SEUs). For this, modular redundancy and runtime partial reconfiguration are commonly employed techniques. However, the reported solutions feature different tradeoffs in the area overhead and the fault latency. In this paper, we propose a low area-overhead SEU recovery mechanism and describe its application in different self-recoverable architectures, which are experimentally evaluated using a specially designed fault-emulation environment. The environment enables the user to inject faults at selected locations of the configuration memory and experimentally evaluate the reliability of the developed solutions.

A fault injection platform for FPGA-based communication systems

“…Com este método, diversas técnicas de tolerância a falhas foram desenvolvidas e avaliadas com o objetivo de proteger sistemas críticos da ocorrência de SEUs em FPGAs baseados em SRAM [F. L. Kastensmidt et al 2006]. As técnicas mais eficientes, em geral, combinam métodos de prevenção, como TMR (Triple Modular Redundancy), com métodos de correção, como scrubbing, que consiste em reconfigurar periodicamente o dispositivo com uma versão livre de falhas da memória de configuração [Uros Legat et al 2012]. Este conjunto é avaliado, por exemplo, em [F. L. Kastensmidt et al 2001], em que o scrubbing é utilizado para eliminar o acúmulo de falhas que pode deteriorar a eficiência da técnica TMR.…”

Design for built-in FPGA reliability via fine-grained 2-D error correction codes

“…Normally a unit frame consists of 41 words, and each word consists of 32 bits. Configuration data is loaded from configuration frame through internal configuration access port (ICAP) read back bus [7]. The 2D-SRAM array stores the temporal copy of configuration frame data and parity data to execute 2-D ECC.…”

“…Built-in TMR mechanism can accumulate soft errors and produce faulty results when two copies of any module in FPGA fail. An alternate method of cyclic redundancy check (CRC) based configuration read back is used to detect the soft error in recent 7series Xilinx devices (Kintex-7 and Zynq-7000) [7][8][9][10]. The above method relies on external nonvolatile radiation hardened memory which stores the golden copy of configuration data.…”

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

“…A Previous approach based on fine-granularity error masking have been developed in [16], such solution however is only applied to TMR technique on majority voter logic scheme. Vice versa, a first overview of recovery architectures for high computational system based on SRAM-based FPGAs have been presented in [17] and [18].…”