Abstract. An error-recovery method for embedded multi-processor systems on SRAM-based FPGAs is proposed. This method is effective against soft-errors in the configuration memory, such as the errors caused by hIgh energy radiation also known as Single Event Upsets. The error-recovery algorithm performs on-line test of the ~PGA configuration memory and recovers errors using dynamic partial reconfiguration. Processor cores perform a dIstributed recovery procedure. If a failure occurs in the processor currently runOing the recovery algOrithm, another processor core takes the role and performs reconfiguration. Presented case study demonstrates the advantage of the proposed approach.
The application of SRAM-based field-programmable gate arrays (FPGAs) in mission-critical systems requires errormitigation and recovery techniques to protect them from the errors caused by high-energy radiation, also known as single event upsets (SEUs). For this, modular redundancy and runtime partial reconfiguration are commonly employed techniques. However, the reported solutions feature different tradeoffs in the area overhead and the fault latency. In this paper, we propose a low area-overhead SEU recovery mechanism and describe its application in different self-recoverable architectures, which are experimentally evaluated using a specially designed fault-emulation environment. The environment enables the user to inject faults at selected locations of the configuration memory and experimentally evaluate the reliability of the developed solutions.
Mission critical and reliable systems on FPGA require error mitigation and recovery techniques to protect them from the errors caused by high energy radiation also known as Single Event Upsets (SEU). Different solutions have been reported with different trade-off of area-overhead and fault latency. We propose a low area-overhead self-reparable procedure based on an internal error recovery mechanism, which is monitored by an external watchdog timer in the role of diagnostic hardcore. The proposed procedure has been verified by extensive fault emulation experiments.
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