SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs

Cai, Chang; Ning, Bingxu; Fan, Xue; Liu, Tianqi; Ke, Linghong; Chen, Gengsheng; Yu, Jun; He, Ze; Xu, Linhai; Liu, Jie

doi:10.1007/s11432-020-3169-x

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…Xilinx is the largest FPGA manufacturer in the world, and its Virtex families have been widely used in aerospace applications. Among them, the Virtex‐7 series are relatively advanced aerospace FPGAs, which are already in the early stages of aerospace applications Cai et al (2022). Xilinx Virtex‐7 series adopts the columnar architecture with rows and columns consisting of a large number of tiles.…”

Section: Preliminariesmentioning

confidence: 99%

A genetic algorithm‐based on‐orbit self‐repair implementation for SRAM FPGAs

et al. 2022

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The reconfigurable capability of static random-access memory (SRAM) field programmable gate array (FPGA) can be used for its fault self-repair method. As a machine learning method, the genetic algorithm (GA) is an FPGA fault repair method that can be automatically executed on-orbit without any ground support. However, the GAbased fault repair method has disadvantages, such as the dependency on processors, the knowledge requirement for user designs in FPGAs, and the small size of repaired circuits. To address these issues, this paper presents a comprehensive analysis of the FPGA bitstream in the aerospace industry. An accurate on-orbit fault location can be identified by bitstream copying and exhaustive test and the executed area of the GA can be reduced to one tile. In addition, the probability function of the algorithm is optimized, which converts floating-point operations into integer arithmetic operations that are easily implemented in FPGAs without processors. The method is outstanding compared with existing ones, considering: (1) The size of repaired circuits is hundreds of times larger than those from other methods. (2) Its implementations are totally up to FPGAs' own logic, with no requirement for processors. (3) There is no knowledge requirement for user design. (4) It reaches the leading level with a success rate of 81%-93%. The method has been verified by various applications in XC7VX330T, which demonstrates its engineering practicability.

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Section: Preliminariesmentioning

confidence: 99%

A genetic algorithm‐based on‐orbit self‐repair implementation for SRAM FPGAs

et al. 2022

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“…In Wang et al (2020), the complex network's Single Event Effect (SEE) fault sensitivity of field-programmable gate array (FPGA) circuits has been analyzed, highlighting its cause and occurrence. SEU and SEE sensitivity of FPGA have been, respectively, presented in Cai et al (2022) and Cai et al (2019), briefing its logical relation impact. The microprocessor's sensitivity failure due to control, execution, combination and sequential logic has been presented in Saggese et al (2005).…”

Section: Introductionmentioning

confidence: 99%

Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

Chitra

2022

COMPEL

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Purpose The purpose of this study is to extend a sensitivity-based reliability technique for the processors deployed in industrial drive (ID). Design/methodology/approach The processor provides flexible operation, re-configurability, and adaptable compatibility in industrial motor drive system. A sensitivity-based model allows a robust tool for validating the system design. Sensitivity is the probability of a partial failure rate for a distributed variable; sensitivity and failure rates are also complementary. Conversely, traditional power electronic components reliability estimating standards have overlooked it, and it is essential to update them to account for the sensitivity parameter. A new sensitivity-based reliability prediction methodology for a typical 32-bit microprocessor operating at 30ºC deployed in ID is presented to fill this gap. The proposed techniques are compared with the estimated processor reliability values obtained from various reliability standards using the validated advanced logistics development tool. The main contribution of this work is to provide a sensitivity extended reliability method over the conventional method directing toward improving reliability, availability, and maintainability in the design of ID. Findings The analysis shows that the sensitivity of the processor’s circuit increases due to increases in complexity of the system by reducing the overall mean time between failure upon comparing among conventional reliability standards. Originality/value The significance of this paper lies in the overall, sensitivity-based reliability technique for processors in comparison to the traditional reliability complexity in IDs.

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Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM

Cai,

Liu,

et al. 2023

IEEE Trans. Device Mater. Relib.

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SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs

Cited by 4 publications

References 7 publications

A genetic algorithm‐based on‐orbit self‐repair implementation for SRAM FPGAs

A genetic algorithm‐based on‐orbit self‐repair implementation for SRAM FPGAs

Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM

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