SEU-tolerant SRAM design based on current monitoring

Vargas, F.; Nicolaidis, M.

doi:10.1109/ftcs.1994.315652

Cited by 93 publications

(42 citation statements)

References 11 publications

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“…Our placement approach can be used with both cell-hardening [Derhacobian et al 2004;Vargas and Nicolaidis 1994] and ECC protection [Chen and Hsiao 1984;Derhacobian et al 2004] techniques. In cases of cell-hardening, there is no need for any extra hardware to maintain partial protection.…”

Section: Architectural Support For Partial Memory Protectionmentioning

confidence: 99%

“…Vargas and Nicolaidis [1994] present a fault-tolerant SRAM design that has a built-in current sensor circuit. This circuit detects the current spikes resulting from SEUs in memory power lines and the correction is performed with the help of a single parity bit.…”

Section: Related Workmentioning

confidence: 99%

“…(In contrast, logic is only exposed to soft errors when it is actively computing a result, a comparatively tiny fraction of time [Mukherjee et al 2003]. ) As a result, several widely adopted techniques have been developed for memory protection [Bossen and Hsiao 1980;Cardarilli et al 2003;Chen and Hsiao 1984;Saleh et al 1990;Vargas and Nicolaidis 1994]. In general, these techniques impose moderate to high levels of power, area, and performance overhead on the system.…”

Section: Introductionmentioning

confidence: 99%

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Exploiting selective placement for low-cost memory protection

Mehrara

Austin

2008

ACM Trans. Archit. Code Optim.

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Many embedded processing applications, such as those found in the automotive or medical field, require hardware designs that are at the same time low cost and reliable. Traditionally, reliable memory systems have been implemented using coded storage techniques, such as ECC. While these designs can effectively detect and correct memory faults such as transient errors and single-bit defects, their use bears a significant cost overhead. In this article, we propose a novel partial memory protection scheme that provides high-coverage fault protection for program code and data, but with much lower cost than traditional approaches. Our approach profiles program code and data usage to assess which program elements are most critical to maintaining program correctness. Critical code and variables are then placed into a limited protected storage resources. To ensure high coverage of program elements, our placement technique considers all program components simultaneously, including code, global variables, stack frames, and heap variables. The fault coverage of our approach is gauged using Monte Carlo fault-injection experiments, which confirm that our technique provides high levels of fault protection (99% coverage) with limited memory protection resources (36% protected area).

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Section: Architectural Support For Partial Memory Protectionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exploiting selective placement for low-cost memory protection

Mehrara

Austin

2008

ACM Trans. Archit. Code Optim.

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“…This possibility was first noted in Vargas et al [1993] where the use of BICS was proposed as a means to identify the occurrence of SEUs in digital circuits. BICS used in combination with a per-word parity bit was subsequently proposed in Vargas et al [1994] and Calin et al [1995] for SRAM protection. In these proposals, BICS were placed on the power lines of the memory.…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of memories protected with BICS and a per-word parity bit

Reviriego

Maestro

Bleakley

2010

ACM Trans. Des. Autom. Electron. Syst.

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This article presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this article allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.

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“…Reliable devices together with fault-tolerance and test strategies are used in order to accomplish this target. In the past few years, strategies to improve the dependability features of reconfigurable computer systems, have been proposed and implemented [1,[7][8][9][10][11][12]. These strategies are mainly based on the traditional ones used in microprocessor based systems.…”

Section: Introductionmentioning

confidence: 99%

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Bezerra

Vargas

Gough

2001

Journal of Electronic Testing

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Abstract. This paper revises and introduces to the field of reconfigurable computer systems, some traditional techniques used in the fields of fault-tolerance and testing of digital circuits. The target area is that of on-board spacecraft electronics, as this class of application is a good candidate for the use of reconfigurable computing technology. Fault tolerant strategies are used in order for the system to adapt itself to the severe conditions found in space. In addition, the paper describes some problems and possible solutions for the use of reconfigurable components, based on programmable logic, in space applications.

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SEU-tolerant SRAM design based on current monitoring

Cited by 93 publications

References 11 publications

Exploiting selective placement for low-cost memory protection

Exploiting selective placement for low-cost memory protection

Reliability analysis of memories protected with BICS and a per-word parity bit

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