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ISBN: 0818655208We present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error correction

NUMBER OF PAGES: xii+1011This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction

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This paper presents the architecture of a CMOS static RAM which is tolerant to radiation-induced upsets. It employs transient current sensing circuits to achieve concurrent, event-driven SEU detection and correction. Tests with simulated upsets and preliminary radiation tests showed the detection of all upsets and proved the effectiveness of the approach