1998
DOI: 10.1007/978-1-4757-6069-9_1
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On-line Testing for VLSI—A Compendium of Approaches

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Cited by 67 publications
(50 citation statements)
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“…As it is shown in Figure 1, in case of a delayed response arrival, after the triggering edge of the system clock CLK, the memory element will capture an erroneous value and a timing error is generated. Various timing error detection techniques have been proposed in the open literature [6][7][8][9][10][11] that are based on the delayed response of timing faults to provide error tolerance using time redundancy techniques. A well known error detection scheme is based on the use of a comparator that is realized by a simple XOR gate [8][9]11].…”
Section: Timing Error Detection and Correctionmentioning
confidence: 99%
“…As it is shown in Figure 1, in case of a delayed response arrival, after the triggering edge of the system clock CLK, the memory element will capture an erroneous value and a timing error is generated. Various timing error detection techniques have been proposed in the open literature [6][7][8][9][10][11] that are based on the delayed response of timing faults to provide error tolerance using time redundancy techniques. A well known error detection scheme is based on the use of a comparator that is realized by a simple XOR gate [8][9]11].…”
Section: Timing Error Detection and Correctionmentioning
confidence: 99%
“…The theory for this offline test approach is well developed and these tests usually achieve good coverage, since having complete control over the system facilitates good testability. Online testing, in contrast, is transparently performed while the SUT is still providing its service [13]. The main advantages of continuous online testing are its very fast detection of errors-as compared with offline tests that are usually performed after long periods of (untested) system operation only-and the continuous collection of a comprehensive and representative test record for statistical assessment and projections.…”
Section: Online Versus Offline Testingmentioning
confidence: 99%
“…Generally, in mission-critical space applications combinational circuits are protected by using duplication/triplication and concurrent-error detection (CED) [3]. However, these methods have too high delay, area and power overheads to be used in commercial applications.…”
Section: Introductionmentioning
confidence: 99%