Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Dhillon, Y.S.; Diril, A.U.; Chatterjee, Abhijit

doi:10.1007/978-1-4020-6488-3_28

Cited by 16 publications

(16 citation statements)

References 11 publications

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“…In [2,25] once sensitive nodes have been identified, resizing the transistors diminishes the likelihood of that node producing an error by reducing the susceptibility to radiation and noise. In [6] a number of parameters can be changed, including voltages and sizings to decrease the susceptibility to noise and radiation based on a similar sensitivity analysis.…”

Section: Motivationmentioning

confidence: 99%

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Ness

Hescott

Lilja

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Deep submicron technology is expected to be plagued by many reliability issues including soft errors in logic. To address this, we demonstrate how exploiting the natural fault masking characteristics of logical functions can be achieved by exploring the design space for selecting subsets of cells from within a cell library prior to synthesis. Subset selection alone is shown to improve the reliability of combinational logic circuits by more than 35%. We compare how subset libraries effect the trade-offs between reliability, area, power, and performance. Further, we show that added benefits of reduced cell library size can benefit the design.

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Section: Motivationmentioning

confidence: 99%

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Ness

Hescott

Lilja

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…The pulse width for all cases measured at half maximum before vanishing is almost constant and is around 30ps.The difference in Q crit values for an SET observed at the site of a strike versus a strike which can propagate an SET to the 8th inverter ahead is 26% for an INV, 21% for a NAND and 16% for a NOR. These small values of transient inducing charges and small differences in minimum charges required to propagate SETs to various stages has implications for SET mitigation techniques which rely on gate sizing to improve reliability, such as [3], [4], and [12].…”

Section: Critical Charge Concepts For Combinational Gatesmentioning

confidence: 99%

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Naseer

Draper

Boulghassoul

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SETinduced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm 2 /mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

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“…Recently, a lot of attention has been given to calculating the soft error rate (SER) of a digital circuit [Zhang et al 2006;Miskov-Zivanov and Marculescu 2006;Zhang and Shanbhag 2004;Dhillon et al 2005]. Most proposed techniques primarily model masking mechanisms such as logic masking, electrical masking, and latching-window masking in various levels of electrical detail [Shivakumar et al 2002].…”

Section: Introductionmentioning

confidence: 99%

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

Krishnaswamy

Viamontes

Markov

et al. 2008

ACM Trans. Des. Autom. Electron. Syst.

126

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We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate variables and eliminate redundant variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM framework for reliability computation. We further define a susceptibility measure to identify gates whose errors are not well masked. We show that hardening a few gates can significantly improve circuit reliability.

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Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Abstract: Abstract

Cited by 16 publications

References 11 publications

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

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