Shakti-T

Menon, Arun; Murugan, Subadra; Rebeiro, Chester; Gala, Neel; Kamakoti, V.

doi:10.1145/3092627.3092629

Cited by 38 publications

(9 citation statements)

References 30 publications

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“…In addition to the research mentioned in [12], there are several new research on security ISA extension. Menon et al [51] developed a RISC-V 64 bit processor Shakti-T, which supports a customized ISA extension containing 8 new instructions for temporal and spatial memory attack protection. Das et al [62] developed another RISC-V processor Shakti-MS.…”

Section: H Securitymentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: H Securitymentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…The work in [13] is an example of how the openness of RISC-V enables academia to work on systematic approaches to eliminating attack surfaces instead of fixing specific security holes and provide strong security guarantees against cache timing and memory access pattern attacks. Another example is [14], which proposes an extension of RISC-V against temporal and spatial memory attacks.…”

Section: Securitymentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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“…Pure software solutions like [28] and [29] can be combined to tackle most kinds of spatial and temporal attacks, but this approach leads to high code size and runtime overheads of around 116% [29]. On the other hand, hardware solutions like [23,25] reduce the run time overhead at the cost of hardware complexity. Although [23] enhances a RISC-V processor to efficiently implement memory checks, the software support required for [23] is extremely complex.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, hardware solutions like [23,25] reduce the run time overhead at the cost of hardware complexity. Although [23] enhances a RISC-V processor to efficiently implement memory checks, the software support required for [23] is extremely complex. Watchdog [25], is a compiler plus hardware solution for memory safety.…”

Section: Introductionmentioning

confidence: 99%

“…It requires lightweight modifications in the compiler to insert certain instructions that enable the hardware to perform the required memory checks at runtime. Further, unlike [25], we are not using any separate shadow memory space and unlike [23], there are no additional tables or tag bits that are required in the processor to store pointer metadata. These features reduce the hardware complexities and storage overhead to a great extent.…”

Section: Introductionmentioning

confidence: 99%

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SHAKTI-MS: a RISC-V processor for memory safety in C

Das

Unnithan

Menon

et al. 2019

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems

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In this era of IoT devices, security is very often traded off for smaller device footprint and low power consumption. Considering the exponentially growing security threats of IoT and cyber-physical systems, it is important that these devices have built-in features that enhance security. In this paper, we present Shakti-MS, a lightweight RISC-V processor with built-in support for both temporal and spatial memory protection. At run time, Shakti-MS can detect and stymie memory misuse in C and C++ programs, with minimum runtime overheads. The solution uses a novel implementation of fat-pointers, those associate capabilities with every pointer. Our proposal is to use stack-based cookies for crafting fat-pointers instead of having object-based identifiers. We store the fat-pointer on the stack, which eliminates the use of shadow memory space, or any table to store the pointer metadata. This reduces the storage overheads by a great extent. The cookie also helps to preserve control flow of the program by ensuring that the return address never gets modified by vulnerabilities like buffer overflows. Shakti-MS introduces new instructions in the microprocessor hardware, and also a modified compiler that automatically inserts these new instructions to enable memory protection. This co-design approach is intended to reduce runtime and area overheads, and also provides an end-to-end solution. The hardware has an area overhead of 700 LUTs on a Xilinx xcvu095-ffva2104-2-e FPGA and 4100 cells on an open 55nm technology node. The clock frequency of the processor is not affected by the security extensions, while there is a marginal increase in the code size by 11% with an average runtime overhead of 13%.

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Shakti-T

Cited by 38 publications

References 30 publications

RISC-V Instruction Set Architecture Extensions: A Survey

RISC-V Instruction Set Architecture Extensions: A Survey

Leveraging the Openness and Modularity of RISC-V in Space

SHAKTI-MS: a RISC-V processor for memory safety in C

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