Shallow and Deep Trench Isolation for use in RF-Bipolar IC:s

Forsberg, Markus; Bormander, C.; Johansson, Tim; Ko, Tai Chuan; Liu, W.; Vellaikal, M.; Cheshire, A.

doi:10.1109/essderc.2000.194752

Cited by 12 publications

(2 citation statements)

References 3 publications

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“…Then, shallow and deep trench isolations are formed as described in Ref. [7]. After oxidation, the collector plug is made using a phosphorus implant.…”

Section: Fabrication Of the Devicementioning

confidence: 99%

A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base

Pejnefors

Johansson²,

Wittborn³

et al. 2002

32nd European Solid-State Device Research Conference

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A self-aligned double poly-Si process using nonselective epitaxy of SiGe:C for the intrinsic base and a dual stack of poly-Si and poly-SiGe for the extrinsic base is presented. Self-alignment of the extrinsic base is obtained by detailed control of the emitter window etch procedure. The etch of the extrinsic base is endpointed at the poly-Si/poly-SiGe interface, and is followed by a timed etch of the SiGe film. Due to the selectivity towards Si, the etch can be stopped at the epitaxial Si surface.The SiGe:C epitaxy is obtained using ultra-high vacuum chemical vapor deposition (UHV/CVD). As a result of the slightly higher growth rate of the epitaxial film compared to the polycrystalline material, an almost planar surface could be obtained.Working devices have been verified by electrical measurements.

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“…Then, shallow and deep trench isolations are formed as described in Ref. [7]. After oxidation, the collector plug is made using a phosphorus implant.…”

Section: Fabrication Of the Devicementioning

confidence: 99%

A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base

Pejnefors

Johansson²,

Wittborn³

et al. 2002

32nd European Solid-State Device Research Conference

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“…The module has previously been described. 14 Figure 1 shows a schematic of the resulting STI and DTI for a bipolar transistor. Here the module is presented in detail and issues that have arisen during process development are discussed.…”

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confidence: 99%

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

Forsberg

Johansson

Liu

et al. 2004

J. Electrochem. Soc.

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A shallow and deep trench isolation process module for high performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ is presented in detail. The shallow trench is etched prior to the deep trench, allowing the deep trench to be placed self-aligned to the shallow trench edge. By planarizing the polycrystalline silicon deep trench filling using chemical mechanical polishing ͑CMP͒ before etchback, the recess into deep trenches is decreased and polysilicon spacer formation at the active area edges is avoided. The poly CMP is stopped before all polysilicon in the active area is removed, to avoid polysilicon dishing and erosion of oxide on top of nitride on active area. Important issues arising during process development are discussed. Two different slurries were evaluated, which resulted in two different nonuniformities of polysilicon thickness. Nonuniformity transfers partially down to a range of recesses into the deep trenches, but the recesses were much smaller compared to the etchback only. Highdensity chemical vapor deposition was used for shallow trench filling and a direct shallow trench isolation-CMP process was developed. The feasibility of the process module was demonstrated using a 0.25 m, 200 mm bipolar double-poly rf process with optional SiGe epi base. Electrical results from completed transistors are presented to verify the function of the module.All nontrivial integrated electronics involve connecting isolated devices through specific electrical connection paths. The device isolation scheme is, therefore, one of the critical parts for integrated circuit processes. Many different schemes have been developed over the years. Parameters like minimum isolation spacing, surface planarity, defect density, process complexity, and electrical properties ͑dc and high frequency͒ influence the choice of a scheme for the particular application and process technology. Mesa isolation, junction isolation, and localized oxidation of silicon ͑LOCOS͒ are techniques in use. As feature sizes continue to decrease, there is a need to reduce shortcomings, such as low packing density, high leakage currents, and latch-up between devices, associated with older isolation technologies.In complementary metal-oxide-semiconductor ͑CMOS͒ technology, LOCOS has been replaced by shallow trench isolation ͑STI͒. 1,2 The lateral encroachment into the active area when using LOCOS, due to oxidation under the nitride at the edges, can be avoided by using STI. Thereby, the lateral control increases, tighter design rules can be applied, and parasitic capacitances are reduced. STI also offers a more planar surface and the possibility to increase the field oxide thickness.A complexity in high-performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ processes is the integration of STI with deep trench isolation ͑DTI͒. Deep trenches, usually with a depth larger than a couple of micrometers, are mainly used to isolate different devices and device groups ͑wells͒ in CMOS/ BiCMOS technology. The trenches are filled with oxide...

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