Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

Tilke, A.; Stapelmann, C.; Eller, M.; Bach, K.H.; Hampp, R.; Lindsay, Richard; Conti, Richard; Wille, W.; Jaiswal, R.; Galiano, M.; Jain, Arpan

doi:10.1109/tsm.2007.896632

Cited by 17 publications

(4 citation statements)

References 9 publications

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“…R and T can both reach as low as 5% (corresponding to η 1 =0.9) with FF=0.9 and Λ = 0.68 µm. For such small trenches each with an aspect ratio of ∼ 5, a high aspect ratio process (HARP) [10] may be required to fill the trenches with SiO 2 . T@FF=0.85 T@FF=0.9 T@FF=0.95 R@FF=0.85 R@FF=0.9 R@FF=0.95 η 1 @FF=0.9…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

High efficiency grating couplers based on shared process with CMOS MOSFETs

Qiu¹,

Sheng²,

Li³

et al. 2013

Chinese Phys. B

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Section: Simulation Results and Discussionmentioning

confidence: 99%

High efficiency grating couplers based on shared process with CMOS MOSFETs

Qiu¹,

Sheng²,

Li³

et al. 2013

Chinese Phys. B

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“…The 90 nm technology was the first node in which performance enhancement was done using stressors [29]. These stressors can be STI [30], Stress Memorization layers [31], nitride located under D1 that was also used as Contact Etch-Stop Layer (cSEL) [32] and eSiGe (elevated SiGe) [33]. Stress induced by the salicided Source-Drain active area can also improve performance [34].…”

Section: Leakage Reduction In Transistor Level-cmos and Srammentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed

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“…After the exposed nitride is removed in a hot-phosphoric bath, well implants are performed, followed by gate oxidation and gate electrode formation. In this process, STI stress builds up during subsequent temperature-ramps due to the mismatch between thermal expansion coefficients of silicon and oxide [14].…”

Section: A Process Of Stimentioning

confidence: 99%

Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization

Xue

Deng

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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With the continuous shrinking of feature size, various effects due to shallow-trench-isolation (STI) stress are becoming more and more significant. The resulting nonuniform distribution of stress affects the MOSFET characteristics and hence changes the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on performance of RF/analog circuits based on layout design and process information. An accurate and efficient FEM-based stress simulator has been developed to handle the layout dependence. A comprehensive MOSFET model is also proposed to capture the effects of STI stress on mobility, threshold voltage, and leakage current. The influence of layout-dependent STI stress on the circuit performance is further studied, and the corresponding optimization strategies to circuit design are discussed. A realistic PLL design realized using 90nm CMOS technology is used as a test case for the proposed approach. . IntroductionAs CMOS technology is moving to sub-90nm nodes, the mechanical stress, which is used to be the secondary concern of the circuit design, now becomes one of the major factors determining circuit performance. Different from other intentional mechanical stresses, STI stress, which is exerted by STI wells on active region of the device, is inevitably formed and has increasingly significant impact on device behavior, especially in aggressively scaled-down CMOS technology.A few papers [1][2][3][4][5] have reported the influence of STI stress on device characteristics. In [6-8], some empirical models have been proposed, which mainly focus on relatively simple cases. Moreover, these studies are all conducted at device level, and thus do not consider the effects on MOSFET characteristics due to complex STI stress distribution on a real die. It is desirable to develop an accurate and efficient method to analyze the influence of the STI stress on device/circuit performance comprehensively at a full-chip level.Mobility change, which is responsible for the driving current and many other device behaviors, is one of the most important factors induced by STI stress. The most widely used Berkeley Short-channel IGFET Model (BSIM) SPICE model (revision 4.6 and higher) does not fully consider the influence of two-dimensional (2-D) STI stress. Recently, Kahng proposed a model that relates the transistor mobility to stress induced by the width of STI regions [9-10]. However, this model focuses only on simplistic situations, so it cannot be applied to complex layout analysis.Leakage current grows significantly with the ever-shrunk gate length, and it is also affected significantly by STI stress. In [11][12], the effects of the STI stress on leakage current at 130nm and 65nm nodes have been discussed. However, to our knowledge, quantitative analysis and models on these effects are not available.Besides, the circuit performance will change under the influence of STI stress. The delay of digital circuits under the influence of the width change of STI is studied in [10] and [13]. However,...

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Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

Cited by 17 publications

References 9 publications

High efficiency grating couplers based on shared process with CMOS MOSFETs

High efficiency grating couplers based on shared process with CMOS MOSFETs

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization

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