Short-Channel Effects in MOSFETs

Khanna, Vinod Kumar

doi:10.1007/978-81-322-3625-2_5

Cited by 44 publications

(21 citation statements)

References 9 publications

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“…The short channel effects (SCE) are known as one of the most critical issues when scaling CMOS devices [24]. To alleviate the SCEs, shallow junction has been conceived, introducing source and drain extension doping beside the channel [25].…”

Section: Channel Doping Engineering To Mitigate Short Channel Effectsmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

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Section: Channel Doping Engineering To Mitigate Short Channel Effectsmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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“…Scaling down the size of transistors has come at a cost due to issues like short channel effects, increased leakage current, decreased reliability and low yield [1,2].To overcome these limitations, FinFETs (Fin Field Effect Transistors) are introduced as 3D transistors mitigating the short channel effects in planar MOSFETs by providing enhanced electrostatic control over the channel, better switching characteristics with a reasonable increase in the production cost [3]. Strain engineering has proven to increase the carrier mobility, which in turn extends the scaling limits and improves the electrical performance [4].…”

Section: Introductionmentioning

confidence: 99%

Linearized radially polarized light for improved precision in strain measurements using micro-Raman spectroscopy

Prabhakara

Nuytten²,

Bender³

et al. 2021

Opt. Express

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Strain engineering in semiconductor transistor devices has become vital in the semiconductor industry due to the ever increasing need for performance enhancement at the nanoscale. Raman spectroscopy is a non-invasive measurement technique with high sensitivity to mechanical stress that does not require any special sample preparation procedures in comparison to characterization involving transmission electron microscopy (TEM), making it suitable for inline strain measurement in the semiconductor industry. Indeed at present, strain measurements using Raman spectroscopy are already routinely carried out in semiconductor devices as it is cost effective, fast and non-destructive. In this paper we explore the usage of linearised-radially polarised light as an excitation source, which does provide significantly enhanced accuracy and precision as compared to linearly polarised light for this application. Numerical simulations are done to quantitatively evaluate the electric field intensities that contribute to this enhanced sensitivity. We benchmark the experimental results against TEM diffraction-based techniques like nano-beam diffraction and Bessel diffraction. Differences between both approaches are assigned to strain relaxation due to sample thinning required in TEM setups, demonstrating the benefit of Raman for nondestructive inline testing.

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“…Different serious issues such as drain-induced barrier lowering, velocity saturation, increase in leakage current, mobility reduction, hot carrier effects and process variation are the side effects of the scaling, which degrade the performance of the circuits. Various solutions have been given to reduce the SCEs, such as reduction in gate oxide thickness and using high dielectric materials in place of SiO2 (Khanna, 2016).…”

Section: Introductionmentioning

confidence: 99%

Leakage reduction technique for nano-scaled devices

Birla

Mahanti

Singh

2020

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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Short-Channel Effects in MOSFETs

Cited by 44 publications

References 9 publications

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Linearized radially polarized light for improved precision in strain measurements using micro-Raman spectroscopy

Leakage reduction technique for nano-scaled devices

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