Should FPGAS abandon the pass-gate?

Chiasson, Charles; Betz, Vaughn

doi:10.1109/fpl.2013.6645511

Cited by 58 publications

(25 citation statements)

References 13 publications

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“…We investigate three technology nodes, 22nm, 45nm and 180nm using the PTM model [24]. The transistor-level circuit designs of SRAMs, FFs and multiplexers are derived from [20]. We model routing wire segments with a one-level π-type RC models and the wire parameters are derived from ITRS [22].…”

Section: A Methodologymentioning

confidence: 99%

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FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Tang

Gaillardon

Micheli

2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-Mainstream Field Programmable Gate Array(FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models. The power consumption of the programmable resources of FPGAs is highly sensitive to their configurations. Due to their highly flexible nature, the configurations of FPGAs routing multiplexers or Look Up Tables (LUTs) are really different from a design to another but current analytical power models cannot accurately capture the associated power differences. In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language. Our power estimation engine automatically generates accurate SPICE netlists according to the FPGA configurations and enables precise power analysis of FPGA architectures. SPICE testbenches can be generated at different level of complexity, denoted as fullchip-level, grid-level and component-level testbenches. Full-chiplevel testbenches dump the netlists associated with the complete FPGA fabric. To reduce simulation time, FPGA-SPICE can split the full-chip-level testbenches into grid-level testbenches, each of which consisting of a complete logic block netlist, or componentlevel testbenches, which consider individual circuit elements, i.e., multiplexers, LUTs, flip-flops, etc., separately. We show that the grid/component-level approach can achieve 14× speed-up with a moderate 14% accuracy loss, compared to the full-chip level. We also use FPGA-SPICE to study the power characteristics of a commercial FPGA architecture at different technology nodes. Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs and flip-flops.

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Section: A Methodologymentioning

confidence: 99%

“…Fig. 6 illustrates the transistor-level circuit design of a LUT considered in this paper, including SRAMs, decoded multiplexers, and buffers [20]. The following XML properties are used to describe the circuit characteristics of the implementation in Fig.…”

Section: ) Look-up Tablesmentioning

confidence: 99%

FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Tang

Gaillardon

Micheli

2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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“…RRAM-based multiplexers are derived from [5]. SRAM-based multiplexers are built with transmissiongates, which are more robust in near-Vt regime compared to pass-transistors [17]. SRAM-based multiplexers employ a treelike structure for a fair comparison with the RRAM-based multiplexers.…”

Section: A Methodologymentioning

confidence: 99%

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Tang

Gaillardon

Micheli

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-Vt SRAM-based FPGA, respectively.

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“…Delay is taken as a weighted sum of the delay of each subcircuit and the weighting scheme is chosen based on the frequency with which each subcircuit was found on the critical paths of placed and routed benchmark circuits. In [19], the lack of a critical path is confronted by simply optimizing each subcircuit individually. As we will describe in more detail in Section VI, COFFE can be configured to use either of these two approaches.…”

Section: Transistor Sizing For Fpgasmentioning

confidence: 99%

“…COFFE can be configured to choose transistor sizes that minimize either the global cost or the local cost. The global cost is some product of total tile area and representative path delay (as in [12]) while the local cost is a product of this particular subcircuit's area and delay (as in [19]). Once the best cost sizing combination has been selected, COFFE checks if the solution is on the boundaries of the initial sizing ranges.…”

Section: B Topology Dependence Of Transistor Resistancementioning

confidence: 99%

COFFE: Fully-automated transistor sizing for FPGAs

Chiasson

Betz

2013

2013 International Conference on Field-Programmable Technology (FPT)

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Abstract-In this paper, we present COFFE (Circuit Optimization For FPGA Exploration), a new fully-automated transistor sizing tool for FPGAs. Automated transistor-level CAD tools are an important part of the architecture exploration flow because they provide accurate area and delay estimates of low-level FPGA circuitry, which must be obtained for each architecture. We show that modeling transistors as linear resistances and capacitances as has been done in previous FPGA transistor sizing tools is highly inaccurate for fine-grained transistor-level design in advanced process nodes. Therefore, COFFE's transistor sizing algorithm maintains circuit non-linearities by relying exclusively on HSPICE simulations to measure delay. Area is estimated with a transistor size-based model that incorporates a number of improvements to enhance its accuracy in advanced process technologies versus prior methods. In addition to more accurate area and delay estimation, COFFE considers more layout effects than prior published work by automatically accounting for transistor and wire loads, which are computed based on architectural parameters and layout area. This new FPGA transistor sizing tool requires only several hours to produce high-quality transistor sizing results for an entire FPGA tile; a task that would normally take months of manual effort. We demonstrate COFFE's utility in FPGA architecture studies by investigating an important new architectural question at the logic-to-routing interface.

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Should FPGAS abandon the pass-gate?

Cited by 58 publications

References 13 publications

FPGA-SPICE: A simulation-based power estimation framework for FPGAs

FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

COFFE: Fully-automated transistor sizing for FPGAs

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