Si interposer build-up options and impact on 3D system cost

Velenis, Dimitrios; Detalle, Mikael; Marinissen, Erik Jan; Beyne, Eric

doi:10.1109/3dic.2013.6702367

Cited by 5 publications

(4 citation statements)

References 13 publications

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“…Active interposers are preferably implemented using mature technology nodes, i.e., for commercial cost savings, yield, and, even more importantly for our work, ease of access to an established and trusted facility. Regarding manufacturing and integration cost, we note that both sides have been argued for, i.e., interposers are cheaper than 3D ICs [18] versus interposers are more costly [26]. However, once system-level cost are considered, the interposer technology remains promising, also because active interposers improve testability [20], [24], [25] and, thereby, allow to better manage yield of the final system.…”

Section: 5dmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

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Section: 5dmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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“…68 Alternatively, the drive for greater circuit densities and functionalities may be satisfied by the use of 3D approaches. 69,70,71,72,73,74 …”

Section: Photolithographymentioning

confidence: 99%

“…The use of this much shorter wavelength brings many additional complexities, and therefore higher costs, as far as the lithography tool is concerned, but can, in principle, reduce the mask complexity thereby reducing the overall cost of ownership. , The final result will depend on whether a suitable combination of resist sensitivity and illumination power can be reached to deliver economically viable throughputs . Alternatively, the drive for greater circuit densities and functionalities may be satisfied by the use of 3D approaches. − …”

Section: Photolithographymentioning

confidence: 99%

Nanomanufacturing: A Perspective

2016

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Nanomanufacturing, the commercially-scalable and economically-sustainable mass production of nanoscale materials and devices, represents the tangible outcome of the nanotechnology revolution. In contrast to those used in nanofabrication for research purposes, nanomanufacturing processes must satisfy the additional constraints of cost, throughput, and time to market. Taking silicon integrated circuit manufacturing as a baseline, we consider the factors involved in matching processes with products, examining the characteristics and potential of top-down and bottom-up processes, and their combination. We also discuss how a careful assessment of the way in which function can be made to follow form can enable high-volume manufacturing of nanoscale structures with the desired useful, and exciting, properties.

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“…Traditionally, fabrication of 2.5-D TSI consists of through silicon vias (TSVs), frontside Cu-damascene interconnects, frontside microbumps, backside reveal (BSR) processing followed by the fabrication of larger backside solder bump before the wafers are passed to the interposer assembly on package. 2.5-D TSI cost [2], [3] reduction can be achieved by increasing throughput and reusing the existing semiconductor and outsourced semiconductor assembly and test (OSAT) tools. We investigate the following options to reduce the TSI cost: 1) by adapting polymer-based Cu-RDL lines; 2) leveraging GHI-lithography; and 3) eliminating the organic substrate and placing the 2.5-D TSI directly on the PCB.…”

mentioning

confidence: 99%

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Katti

et al. 2015

IEEE Des. Test

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h TWO-AND-A-HALF-DIMENSIONAL THROUGH SILICON interposers (TSIs) provide an attractive packaging opportunity enabling the integration of off-the-shelf heterogeneous 2-D integrated circuit (IC) components (i.e., logic and memory) [1] with a plausible extension to build an entire smart system consisting of logic, memory, sensors, photonics, etc., on 2.5-D ICs. While the technology is undisputedly attractive, 2.5-D TSI technology cost is a critical factor to adopt the technology in high volume manufacturing. Traditionally, fabrication of 2.5-D TSI consists of through silicon vias (TSVs), frontside Cu-damascene interconnects, frontside microbumps, backside reveal (BSR) processing followed by the fabrication of larger backside solder bump before the wafers are passed to the interposer assembly on package. 2.5-D TSI cost [2], [3] reduction can be achieved by increasing throughput and reusing the existing semiconductor and outsourced semiconductor assembly and test (OSAT) tools. We investigate the following options to reduce the TSI cost: 1) by adapting polymer-based Cu-RDL lines; 2) leveraging GHI-lithography; and 3) eliminating the organic substrate and placing the 2.5-D TSI directly on the PCB.Two-and-a-half-dimensional TSIs with Cudamascene interconnects are costlier due to chemical mechanical polishing (CMP) costs associated with the fabrication of frontside Cu-damascene interconnects. Polymer-based Cu-RDL interconnects provide a CMPless low-cost fabrication alternative enabling OSATs to fabricate and assemble a 2.5-D low-cost through silicon interposer (LC-TSI) in low-cost infrastructure facilities. Additionally, the cost reduction in 2.5-D TSI fabrication and assembly can be achieved by adapting the GHI-line lithography providing enhanced Editor's notes: Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.throughput. Moreover, placement of 2.5-D TSI directly on the package eliminating an organic substrate reduces the 2.5-D TSI cost even further.Technology specifications and challenges along with LC-TSI fabrication and assembly flow are detailed in the Technology specifications and challenges section and the 2.5-D LC-TSI fabrication and assembly flow section, respectively. Electrical characterization and measurement results are elaborated on in the Electrical characterization and measurements section. Results also include the early reliability test results to evaluate suitable polymer dielectric through unbiased highly accelerated stress test (uHAST). Technology specifications and challengesTypical applications for 2.5-D TSI include SoC/GPU/FPGA integration with different classes of memories such as WIDEIO, high bandwidth memory (HBM), etc. For example, Li et al.[1] detail FPGA as well as guest-die-based TSI integration. Cross section of 2.5-D LC-TSI technology with...

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Si interposer build-up options and impact on 3D system cost

Cited by 5 publications

References 13 publications

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nanomanufacturing: A Perspective

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

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