Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects

Kim, Ilgweon; Han, Sangyeon; Han, Kwangseok; Lee, Jong-Ho; Shin, Hyungcheol

doi:10.1143/jjap.40.447

Cited by 28 publications

(17 citation statements)

References 12 publications

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“…23 Judging from the Q e of the single-layer embedded sample and the nc-ZnO density, in average, each nc-ZnO dot stores about one electron, which is in the same order of magnitude as that of nc-Si in SiO 2 . 24,25 The increase in the charge trapping density from the addition of the second embedded layer is consistent with the increase in the number of the nc-ZnO dots in the dielectric structure. Figure 2a also shows that after a −8 V stress, the C-V curve of the single-layer embedded sample slightly shifts to the negative direction, i.e., ⌬V FB = −0.15 V, which indicates the trap of a small amount of holes.…”

Section: Resultssupporting

confidence: 62%

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO Embedded Zr-Doped HfO[sub 2] High-k Dielectric

Lin

Kuo

2010

Electrochem. Solid-State Lett.

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Metal-oxide-semiconductor memory capacitors composed of dual-layer nanocrystalline ZnO embedded zirconium-doped hafnium oxide high-k film were fabricated, characterized, and compared with those with the single-layer nanocrystalline ZnO embedded sample. Distinct layers of discretely dispersed nanocrystalline dots embedded in the amorphous high-k matrix were observed. The nanocrystalline ZnO dots trap many electrons. The dual-layer sample not only drastically increases the charge storage density but also improves the charge trapping speed due to the coulomb blockade effect. This is a potentially important gate dielectric structure for high density, high speed nonvolatile memories.

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Section: Resultssupporting

confidence: 62%

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO Embedded Zr-Doped HfO[sub 2] High-k Dielectric

Lin

Kuo

2010

Electrochem. Solid-State Lett.

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“…The implementation of silicon-quantum-dots (Si-QDs) as a floating gate in metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been attracting much attention because of its feasibility for multivalued memory operations at room temperature [1][2][3][4]. So far, we have fabricated nMOSFETs with a Si-QDs floating gate and confirmed multistep threshold voltage shift due to Coulomb blockade effect at Si-QDs at room temperature [1,4].…”

Section: Introductionmentioning

confidence: 82%

Characterization of MultiStep Electron Charging to Silicon-Quantum-Dot Floating Gate by Applying Pulsed Gate Biases

Nagai¹,

Ikeda²,

Shimizu³

et al. 2005

Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials

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“…[1][2][3][4][5][6][7][8][9][10][11] Charging and discharging in nc-Si are indeed very important as they are directly related to data storage/retention in the memory cells. For memory applications, the nanocrystals are normally confined in a narrow layer embedded in the gate dielectrics near the Si substrate.…”

mentioning

confidence: 99%

Modulation of Capacitance Magnitude by Charging/Discharging in Silicon Nanocrystals Distributed Throughout the Gate Oxide in MOS Structures

Chen

Liu

et al. 2005

Electrochem. Solid-State Lett.

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In this work, charge trapping in silicon nanocrystals ͑nc-Si͒ distributed throughout the gate oxide in a metal oxide semiconductor ͑MOS͒ structure has been studied. This situation is different from the conventional one with nc-Si confined in a narrow layer embedded in the gate oxide. In the latter, charge trapping in nc-Si leads to a shift in capacitance-voltage characteristic ͑i.e., a change in the flat-band voltage͒. In contrast, in the former the charge trapping leads to a dramatic reduction in the MOS capacitance. The original capacitance could be recovered after the release of the trapped charges by a small bias, UV light illumination, or low-temperature thermal annealing.Silicon nanocrystals ͑nc-Si͒ embedded in gate oxide of metal oxide semiconductor ͑MOS͒ structures are expected to play an important role in memory devices due to the nanocrystals unique charging and discharging effect. [1][2][3][4][5][6][7][8][9][10][11] Charging and discharging in nc-Si are indeed very important as they are directly related to data storage/retention in the memory cells. For memory applications, the nanocrystals are normally confined in a narrow layer embedded in the gate dielectrics near the Si substrate. 9-11 However, it would be interesting to examine the charging and discharging in the nc-Si that distributes throughout the gate dielectrice specially with the nc-Si peak concentration located near the gate. For the MOS structures with such an nc-Si distribution, charging and discharging of the nc-Si are expected to occur easily and thus they will have a significant impact on the electrical characteristics of the MOS structures. Indeed, for such MOS structures, some interesting phenomena have been observed. In a previous study, 12 it was shown that charging in the nc-Si leads to a change in both the gate current and the MOS capacitance, and the change in the oxide conduction is explained by the change in the nc-Si tunneling paths due to charging/discharging in the nc-Si. In the present study, it will be shown that the capacitance can be reduced to an extremely low level by charging up the nc-Si with either a positive or a negative gate bias. Furthermore, the original capacitance can be recovered by discharging the nanocrystals with a small opposite gate bias, ultraviolet ͑UV͒ illumination, or even a low-temperature ͑100°C͒ heating. The modulation of the capacitance magnitude by charging/discharging in the nc-Si provides the possibility of memory devices application.To fabricate the MOS structures with nc-Si distributed throughout the gate oxide with its peak concentration located near the gate, a 30 nm SiO 2 film was thermally grown on p-type ͑100͒ Si wafers in dry oxygen at 950°C. Then Siϩ ions with the dose of 3 ϫ 10 16 cm Ϫ2 were implanted to the SiO 2 at 14 keV. From the transport and range of ions in matter ͑TRIM͒ simulations, the peak concentration was estimated to be at the depth of ϳ20 nm. Thermal annealing was carried out at 1000°C in N 2 ambient for 1 h to induce nc-Si formation. The annealing can also eliminate ...

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Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects

Cited by 28 publications

References 12 publications

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO Embedded Zr-Doped HfO[sub 2] High-k Dielectric

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO Embedded Zr-Doped HfO[sub 2] High-k Dielectric

Characterization of MultiStep Electron Charging to Silicon-Quantum-Dot Floating Gate by Applying Pulsed Gate Biases

Modulation of Capacitance Magnitude by Charging/Discharging in Silicon Nanocrystals Distributed Throughout the Gate Oxide in MOS Structures

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