Si single electron transistor fabricated by chemical mechanical polishing

Abstract

The authors report the results of a novel single electron transistor (SET) fabrication technique that combines the unique advantages of chemical mechanical polishing and the versatility and scalability of silicon processing. A thin (∼15 nm) line of degenerately doped silicon on insulator is embedded in a planarized plasma enhanced chemical vapor deposition oxide through nanoencapsulation. A pit in this line is formed by a highly selective silicon dry etch, and the tunnel oxide is grown on the sidewalls of the pit using rapid thermal oxidation. Degenerately doped amorphous silicon is deposited into the pit to form the SET island, the overburden of silicon is removed, and the structure is thinned down by chemical mechanical polishing. The SET’s charging diagram indicates a charging energy of around 20 meV, credited to its small tunnel junction size as well as possible “puddle” formation from the dopant distribution within the island and the leads. The observed anomalies, such as missing and split diamonds in the charging plots and random telegraph signals, suggest that the donor sites play an important role in the device operation. Several fabricated SETs show a similar Coulomb blockade at 4 K, demonstrating reasonable yield for the process.

Fabrication of nanodamascene metallic single electron transistors with atomic layer deposition of tunnel barrier

“…In this scheme, CMP provides a path for scaling down the dimensions of the tunnel junctions beyond the dimensions imposed by electron beam lithography (EBL) and lift-off, since by careful adjustment of the polish step, the depth (height) of the junctions can be further reduced, and planar tunnel junctions with less than 10 nm in thickness are achievable. 8 The cyclic deposition of ALD, with one monolayer of the desired material deposited in each cycle, makes it a more controllable and precise method to form ultrathin tunnel barriers compared to the formation of the barrier from the native oxide of metal substrates. Recently, a Pt-based SET with thermal ALD Al 2 O 3 tunnel barrier has been reported.…”

Ultrathin titanium passive devices fabrication

“…This process involves a titanium planarization step at the end of the device fabrication. Lee et al have also shown working SETs with either a silicon [5] or an aluminum [6] island using a two steps CMP process. This paper presents electrical characterization of titanium nanowires (NW) fabricated with a modified nanodamascene process.…”

Novel Hybrid SETMOS Logic for Ultra-low-power Applications

“…The low current drive, low supply voltage, small critical dimensions due to aF range total capacitance, and room temperature operations were the issues for CMOS compatibility [5][6][7][8]. However, the past two decades witnessed significant research work to attain and overcome many of these issues [8][9][10][11][12][13][14][15][16][17][18]. Research to exhibit room temperature behavior analogous to a conventional MOSFET and its demonstration for application in logic and memory circuits is still in infancy.…”