The authors report the results of a novel single electron transistor (SET) fabrication technique that combines the unique advantages of chemical mechanical polishing and the versatility and scalability of silicon processing. A thin (∼15 nm) line of degenerately doped silicon on insulator is embedded in a planarized plasma enhanced chemical vapor deposition oxide through nanoencapsulation. A pit in this line is formed by a highly selective silicon dry etch, and the tunnel oxide is grown on the sidewalls of the pit using rapid thermal oxidation. Degenerately doped amorphous silicon is deposited into the pit to form the SET island, the overburden of silicon is removed, and the structure is thinned down by chemical mechanical polishing. The SET’s charging diagram indicates a charging energy of around 20 meV, credited to its small tunnel junction size as well as possible “puddle” formation from the dopant distribution within the island and the leads. The observed anomalies, such as missing and split diamonds in the charging plots and random telegraph signals, suggest that the donor sites play an important role in the device operation. Several fabricated SETs show a similar Coulomb blockade at 4 K, demonstrating reasonable yield for the process.

A novel process for silicon single electron transistors (Si-SET) is presented, combining chemical mechanical polishing (CMP) with the advantages of silicon processing. To eliminate effects caused by random distribution of dopants in the island, The Si-SET’s doped-Si island is replaced with an aluminum or tantalum island by integrating a metal CMP technique with our nano-encapsulation process. The fabricated hybrid Al-island Si-SET has ∼10 nm silicon on insulator lines as the source and drain leads. It shows characteristic Coulomb blockade oscillations with a charging energy of ∼4 meV. The fabrication results demonstrate the scalability of the SET island and the tunnel junction size in a manufacturable top-down approach.

No abstract

No abstract

No abstract