Fabrication of hybrid metal island/silicon single electron transistor

Abstract

A novel process for silicon single electron transistors (Si-SET) is presented, combining chemical mechanical polishing (CMP) with the advantages of silicon processing. To eliminate effects caused by random distribution of dopants in the island, The Si-SET’s doped-Si island is replaced with an aluminum or tantalum island by integrating a metal CMP technique with our nano-encapsulation process. The fabricated hybrid Al-island Si-SET has ∼10 nm silicon on insulator lines as the source and drain leads. It shows characteristic Coulomb blockade oscillations with a charging energy of ∼4 meV. The fabrication results demonstrate the scalability of the SET island and the tunnel junction size in a manufacturable top-down approach.

Ultrathin titanium passive devices fabrication

“…This process involves a titanium planarization step at the end of the device fabrication. Lee et al have also shown working SETs with either a silicon [5] or an aluminum [6] island using a two steps CMP process. This paper presents electrical characterization of titanium nanowires (NW) fabricated with a modified nanodamascene process.…”