Signal Delay in RC Tree Networks

Penfield, P.; Rubinstein, J.

doi:10.1109/dac.1981.1585417

Cited by 108 publications

(16 citation statements)

References 2 publications

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“…This work very nicely compliments the work of Penfield and Rubenstein [8]. They have looked at the problem of estimating delays through RC tree networks and obtained upper and lower bounds which may be computed in linear time.…”

Section: Glitches Hazards and Multiple Input Gatessupporting

confidence: 66%

The Analog Behavior of Digital Integrated Circuits

Glasser

1981

18th Design Automation Conference

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The an'dog behavior of digital VLSI circuits is investigated. A theory based on nonlinear Thevenin equivalent circuits and RC ladder networks is developed. We obtain closed form expressions for the upper and lower bounds on propagation delay through a string of inverters. We generalize this to multiple-input, multiple-output gates and show that the problem of estimating signal propagation delays in, VLSI circuits may be reduced to the problem of summing the step responses of a set of linear RC networks. As well as havhlg implications for a computationally efficient timing simulator, the theory begins lhe formalization of the fundamental properties of digital integrated circuits.

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Section: Glitches Hazards and Multiple Input Gatessupporting

confidence: 66%

The Analog Behavior of Digital Integrated Circuits

Glasser

1981

18th Design Automation Conference

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“…@robabfity density function) [6], where the k-th moment mk exists for any k >0, Ekore used this distribution interpretation of moments to propose the approximation of the median by the first momen~or mean [l ]. Penfield and Rubenstein demonstrated that RC tree impuke responses satisfied the conditions in (4) [9], and the Ehnore delay has been used for delay esdmation ever since.…”

Section: 1: Probability Interpretation Of Momentsmentioning

confidence: 99%

h-gamma

Lin

Acar

Pileggi

1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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Recently a probability interpretation of moments wm proposed as a compromise between the Elmore delay and higher or&r mommt matching for RC timing estimation [5]. By modeling RC impufses as tinze-sht~ed incomplete gamma distribution functions, the delays could be obtained via table 100tip using a gamma integral table and the first three moments of the imptise response. However, while this approximation worti well for many examples, it struggles with responses when the metal resistance becomes dominant, andproduces results with impractical h.meshz~values. In this paper the probability interpretation is etiended to the circuit homogeneous response, without requiring the time shi$ parameter The gamma distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model (RC tree or mesh), the stability of the holtlogetleol{s-gml?ta distribution model is guaranteed. It is demonstrated that when a table model is carefilly constructed the hgamma approxinrationprovides for exellent improvemeti over the Elmore delay in terms of accur~, with ve~little additiond cost in terms of CPU time.

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“…Programs such as RSIM treat MOS transistors as linear resistors and compute signal transition times using the Penfield-Rubenstein technique [PEN81], which is an RC-delay modeling technique. Although the method is extremely efficient, the overall accuracy of this approach is limited due to the simplified nature of the delay model.…”

Section: Switch-level Simulationmentioning

confidence: 99%

Mixed-Mode Simulation

Saleh

Newton²

1990

The Kluwer International Series in Engineering and Computer Science

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Signal Delay in RC Tree Networks

Cited by 108 publications

References 2 publications

The Analog Behavior of Digital Integrated Circuits

The Analog Behavior of Digital Integrated Circuits

h-gamma

Mixed-Mode Simulation

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