Signal-path driven partition and placement for analog circuit

Abstract

Abstract-This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three observations: thinking of hierarchical design for analog, structural feature of circuit based on signal-path, requirements of matching/symmetry constraint and the reduction of parasitics. The thinking of hierarchical design makes the whole analog circuit divided into core-circuit and bias-circuit. So, the algorithm is designed as two independent steps: core-circuit is placed firstly, and then bias-circuit. The structural feature of circuit based on signal-path and the requirement of matching/symmetry constraint decide the placement pattern of core-circuit. The reduction of parasitics requires the algorithm to select the optimal variants to realize the placement. Experimental results demonstrate that this algorithm can generate the compact layout with high performance and it is universal and effective. I IntroductionNowadays, SOC integrates all of the circuits on one chip, including digital and analog parts. The physical design of digital circuits is automated to a large extent but the layout of analog circuits is still a manual, time-consuming and error-prone, which makes custom analog layout be a bottleneck in the mixed-signal design flow. The fast changes of demands in ASIC market also require analog layout automation tool to accelerate the whole design process. Thus, the time from product demands to market can be greatly shortened. Analog placement is a vital step in the design flow from circuit schematics to layout. Analog placement automation tool must not only provide a good rectangle packing functionality, but also satisfy analog specifications. Mismatch and parasitics induced by the layout are the most important factors to affect the performance of analog circuit.In the past two decades, researches have done many researches about analog placement, but no successful commercial products have existed. Generally speaking, the existing methodologies for analog placement automation can be classified into the following several categories.The constructive placement techniques, which adopts the increase placement thinking that one module is selected at a time and positioned in the best available location, which is calculated by an evaluation function or directed by an expert system. A placement tool based on expert knowledge is developed in well with the problem size, but the final placement can be poor because there are no effective methods to decide the order of modules and the view of global optimization and the costs of supporting expert system are expensive.A placement technique iteratively combining min-cut partitioning and force-directed placement (FDP) has been employed in an interactive environment for full-custom designs [2]. This method can fast obtain a feasible placement solution satisfying geometrical constraints but not ensure that the placement is a good placement.Nowadays, the simulated annealing This paper a...

Performance-driven analog placement considering monotonic current paths

“…During placement optimization, most of the recent works applied the simulated annealing algorithm [15], except [11] which is based on a non-stochastic approach. Although the previous works had proposed to handle various analog placement constraints, as seen in Table 1, only Long et al [13] mentioned the importance of the considering current/signal flows during analog placement. Based on the extracted the current/signal paths of an analog circuit, they simply adopted the fixed placement topology with straight current paths, as shown in Figure 1(c), which leads to very limited solution space.…”

“…Although the equivalent channel widths and channel lengths based on these three layouts are the same, the induced source/drain capacitance of each layout is quite different. Figure 2(b) shows the source/drain capacitance of a MOS transistor with respect to the number of fingers in the layout, which is sourced from [13]. Since the difference of the source/drain capacitance of a MOS transistor with different finger numbers can be as large as 40%, it is not allowed to arbitrarily change the finger numbers of the MOS transistors in the critical current/signal paths during placement optimization.…”

“…When placing the MOS transistors with fixed physical dimensions (i.e. fixed finger numbers), which are usually the dimensions of the minimum source/drain capacitance, according to the currentpath constraints, the resulting placement with straight current paths generated by the approach in [13] is no longer compact, which is shown in Figure 3(a). To minimize the layout area, modern analog placement algorithms tend to producing a placement containing nonmonotonic current paths, as shown in Figure 3…”

“…Figure 1(a) shows the schematic of a fully-differential folded-cascode operational amplifier (Op-Amp), which contains four current paths from the power source to ground, as seen in Figure 1(b). To satisfy the current-path constraints in analog placement, Long et al [13] simply placed the MOS transistors in each current path along the predefined straight current path direction from left to right. To minimize the total area of such kind of placement, they tried to adjust the physical dimensions of the MOS transistors in the same current path to the same height, and to make the physical length of all current paths nearly equal.…”

Simultaneous analog placement and routing with current flow and current density considerations

“…Existing analog layout synthesis algorithms focus on one of the two constraints alone: current-flow constraints at the placement stage and current-density constraints at the routing stage. For the currentflow constraints, Long et al proposed a signal-path driven partition and placement method for analog circuits [15], which simply places modules closely from left to right in each signal-path according to the pre-defined sequence to satisfy current-flow constraints. To achieve a more compact placement result, Wu et al introduced a slicing-treebased analog placement representation to generate multiple compact analog placements with current-path constraints [22].…”