Signal probability for reliability evaluation of logic circuits

Single event transient mitigation through pulse quenching: Effectiveness at circuit level

“…In order to evaluate how the reduction in sensitive area translates into reduction in error rate, we have made use of the SPRA method [12]. Its original purpose is to calculate circuit reliability by taking into account logical masking.…”

Precision-aware soft error protection for GPUs

“…If there is no such path due to the circuit inputs applied, soft errors affecting the gate will be logically masked. Since analytical computation of logical masking probabilities is complicated by reconvergent fanouts [6], we implement a statistical approach similar to that in [36] for our baseline selective hardening algorithm. To statistically determine the probability of there being a logically sensitized path from any given gate to the output, we functionally sim- Apply random input vector to circuit; 3: for g ← 1, num gates do 4: Flip output of gate g; 5: if output mantissa changed then 6: gate score[g] += abs((correct output 7: -faulty output)/correct output); 8: end if 9:…”

Reliability evaluation of logic circuits using probabilistic gate models

“…Recent researches have focused on the use of Markov random fields [11], probabilistic model checking (PMC) [12], probabilistic transfer matrices (PTMs) [13], Bayesian networks [14], analytical and scalable approaches [15], probabilistic decision diagrams (PDDs) [16], Boolean difference calculus [17], signal probabilities [18], circuit transformations [19] and multiple passes for sequential circuits [20]. Several of these approaches, such as those using PMC [12], PTMs [13] and PDDs [16], provide accurate evaluation results, however, they are affected by the problems of state space explosion and an exponential complexity, which make them practically infeasible to be used for large circuits.…”

“…Several of these approaches, such as those using PMC [12], PTMs [13] and PDDs [16], provide accurate evaluation results, however, they are affected by the problems of state space explosion and an exponential complexity, which make them practically infeasible to be used for large circuits. While the other techniques can be more efficient in terms of runtime or memory usage [14,15,[17][18][19], they generally provide approximate results. In [14], an approximate inference scheme is proposed for the handling of large circuits using a probabilistic model based on Bayesian networks.…”

“…A novel approach using Boolean difference calculus is applied to the probabilistic analysis of logic circuits in [17]. In [18], several algorithms based on the straightforward application of signal probabilities are presented to estimate circuit reliability. In [19], the signal probabilities of all internal nodes of logic circuits are calculated using techniques of circuit transformation.…”