Signal propagation over perforated reference planes

Shan, Lei; Ritter, Mark B.; Haridass, A.; Weekly, R.; Becker, W.D.; Klink, E.

doi:10.1109/spi.2007.4512222

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…This is consistent with Lei Shan et al who have shown that voids/holes results in signal losses which scale with the size of the voids/hole. In addition, the increased losses with thermal cycling can be caused by compositional changes in the SiO x isolation liner [3]. To further understand the changes in the liner oxide, we used a variety of scanning probe techniques to measure the changes in the electrical properties of the isolation around the Si-TSVs.…”

Section: Resultsmentioning

confidence: 99%

Measurement Science for "More-Than-Moore" Technology Reliability Assessments

et al. 2013

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In this paper, we will present an overview of metrology issues and some of the techniques currently under development in our group at NIST, aimed at understanding some of the potential performance limiting issues in such highly integrated systems. We will discuss our attempts to identify and characterize the various types of defects and relate them to where and why they form, without interrupting the responsible phenomena.

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Section: Resultsmentioning

confidence: 99%

Measurement Science for "More-Than-Moore" Technology Reliability Assessments

et al. 2013

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Slot crossing and non-native IO voltage referencing: Effectiveness of image return capacitance to address signal integrity concerns

Bailey

Bartley

Doyle

et al. 2009

2009 59th Electronic Components and Technology Conference

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There is a growing requirement to thoroughly understand the tradeoffs made in "real-world" applications where package cross sections provide insufficient planes for both desirable IO referencing and DC current delivery. Allowing minimal split crossings and using significant decoupling are widely known design-guide "solutions". It is also well known that slot crossing within any high-speed application should be avoided. This paper will perform a real-world study of current return paths on various carrier referencing structures and quantify, in terms of margin degradation, how concerning slot crossings really are and what can be done to mitigate these losses. This paper will not perform a "text-book" study of slot crossing phenomena; rather it will quantify Signal Integrity tradeoffs in modern, cross-section challenged, high-speed applications.This paper will discuss IO referencing, Signal Integrity, power distribution, decoupling, and cross-section trade-offs within an exemplary system including a high-speed memory application. Analysis will use a real-world example to quantify conventional implementation compromises and how each trade-off impacts performance, cost, design risk, and breaking points. Specifically, this paper will discuss and quantify:1) The effect of interrupted reference planes on high-speed IO as frequency and the number of simultaneous switches varies 2) Margin degradation due to insufficient cross-sections creating mismatched driver IO and implemented reference voltages 3) Effectiveness of image return capacitors against IO referencing VCC that is not native to their driver supply Historical Memory Bus Image Return PathIn early 2004, IBM analyzed a 133 MHz memory bus on a card that was failing in the lab. Analysis of the design soon identified a disrupted image return path in the memory bus. Several slots, passing through all reference and voltage planes, had been formed in the path of the memory signals as they passed beneath a pin-through-hole connector. This occurred due to the size of the via antipads and minimally spaced vias. Further, there was a shortage of voltage and ground vias in close proximity to the signal vias. A selection of ten of the memory nets on that bus are shown in Figure 1. Figure 1. Via slots in 133 MHz Memory BusFailure analysis continued in the lab and it was soon shown that the signals near the center of the slots had higher failure rates than the data nets near the end of the slots. These nets were probed in the lab and it was verified that the signal integrity of the signals degraded as one approached the center of the slot.The memory bus performance was improved by reducing the size of the via antipads. This allowed some copper to remain on the reference planes between the connector pins, thereby reducing the slot. Voltage and ground vias were also added near the signal vias to improve signal integrity. This example reinforced how important image return path is, even at the relatively slow (by today's standards) speed of 133 MHz. Prior Analysis of slot crossingsPa...

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