Silicon auditory processors as computer peripherals

Lazzaro, John; Wawrzynek, John; Mahowald, Misha; Sivilotti, Massimo A.; Gillespie, D.W.

doi:10.1109/72.217193

Cited by 211 publications

(117 citation statements)

References 14 publications

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“…Because AER was originally formulated to emulate the optic nerve (Mahowald, 1994) and the auditory nerve (Lazzaro, Wawrzynek, Mahowald, Sivilotti & Gillespie, 1993), it implements a one-to-one connection topology. To implement more complex neural circuits, convergent and divergent connections are required.…”

Section: Introductionmentioning

confidence: 99%

Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

2001

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We present a scheme for implementing highly-connected, recon®gurable networks of integrate-and-®re neurons in VLSI. Neural activity is encoded by spikes, where the address of an active neuron is communicated through an asynchronous request and acknowledgement cycle. We employ probabilistic transmission of spikes to implement continuous-valued synaptic weights, and memory-based look-up tables to implement arbitrary interconnection topologies. The scheme is modular and scalable, and lends itself to the implementation of multi-chip network architectures. Results from a prototype system with 1024 analog VLSI integrate-and-®re neurons, each with up to 128 probabilistic synapses, demonstrate these concepts in an image processing task. q

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Section: Introductionmentioning

confidence: 99%

Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

2001

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“…For simplicity, the figure only illustrates row arbitration. Column arbitration is carried out in an identical manner Another approach to transmitter design is the use of an arbitration tree to queue temporally overlapping events [6]. Implementations of this approach arrange the neurons in two dimensions in order to exploit locality of spiking activity.…”

Section: Design Trade-offsmentioning

confidence: 99%

Address-Event Communication Using Token-Ring Mutual Exclusion

Imam

Manohar

2011

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems

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Abstract-We present a novel Address-Event Representation (AER) transmitter circuit to communicate pulses of neural activity (spikes) within a neuromorphic system. AER circuits allow an ensemble of neurons to achieve large scale timemultiplexed connectivity through a shared communication channel. Our design makes use of token-ring mutual exclusion where two circulating tokens in a 2D array of neurons provide exclusive access to the shared channel. Compared to traditional arbitration-tree-based designs, our design has a higher throughput and lower latency during high spiking activity. This allows the circuit to serve larger neuronal densities and higher spiking activity while maintaining the temporal precision required by the system. Our design also eliminates the address line loads that restricted scalability in previous designs. In addition, our simpler circuit topology leads to area and power savings.

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“…Input signals may arrive from visual sensors, but also from other neuromorphic sensors representing a wide variety of sensory stimuli obtained from different sources. In this framework, sensory signals are sent to (and from) the selective attention chip in the form of asynchronous binary pulses of fixed height, but with variable inter-pulse intervals (similar to neural spike trains), conforming to the Address-Event Representation (AER) [13,3]. …”

Section: A Neuromorphic Device For Modeling Selective Attentionmentioning

confidence: 99%

Computation in Neuromorphic Analog VLSI Systems

Indiveri

2002

Perspectives in Neural Computing

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In this paper we present an overview of basic neuromorphic analog circuits that are typically used as building blocks for more complex neuromorphic systems. We present the main principles used by the neuromorphic engineering community and describe, as case example, a neuromorphic VLSI system for modeling selective visual attention. Neuromorphic EngineeringThe term "neuromorphic" was coined by Carver Mead to describe very large scale integration (VLSI) systems containing electronic analog circuits that mimic neurobiological architectures present in the nervous system [18]. Neuromorphic computation is related to modeling and simulation of networks of neurons and systems using the same organizing principles found in real nervous system. In recent times the term "neuromorphic" has also been used to describe mixed analog/digital VLSI systems that implement computational models of real neural systems. These VLSI systems, rather than implementing abstract neural networks only remotely related to biological systems, in large part, directly exploit the physics of silicon (and of CMOS VLSI technology) to implement the physical processes that underlie neural computation.Neuromorphic engineering is a new discipline at the boundary between engineering and neuroscience, but which crosses many other fields, including biology, physics, computer science, psychology, physiology, etc.

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Silicon auditory processors as computer peripherals

Cited by 211 publications

References 14 publications

Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

Address-Event Communication Using Token-Ring Mutual Exclusion

Computation in Neuromorphic Analog VLSI Systems

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