Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

Patel, C.S.; Tsang, C. K.; Schuster, Christian; Doany, F. E.; Nyikal, H.; Baks, Christian; Budd, R.; Buchwalter, L.P.; Andry, Paul; Canaperi, D.; Edelstein, D.; Horton, R.; Knickerbocker, John; Krywanczyk, T.; Kwark, Young; Kwietniak, K.T.; Magerlein, J. H.; Rosner, J.; Sprogis, E.

doi:10.1109/ectc.2005.1441439

Cited by 32 publications

(23 citation statements)

References 9 publications

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“…A variety of vertical TSV technologies have been developed by IBM for silicon-carrier applications [19][20][21]. A number of vias-last approaches have been demonstrated, and this process has the advantage that the constituent CMOS technologies in the 3D stack do not need to be modified, because the TSV is formed only after assembly by using backside deep reactive-ion etching.…”

Section: Vertical Interconnectmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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Section: Vertical Interconnectmentioning

confidence: 99%

Wafer-level 3D integration technology

et al. 2008

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“…One test site focused on design of a high speed electrical-optical transceiver operating at an aggregate bandwidth of 1 Tbit/sec [15]. This test site explored high speed differential microstrip lines that could operate in 10-20 GHz frequency range with less than 5 dB/cm transmission losses.…”

Section: Wiringmentioning

confidence: 99%

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Several papers have been published recently by IBM research that introduced the silicon carrier technology for a wide range of twoand three-dimensional product applications and presented detailed descriptions of its key technology enablers [2,5,7,15,16,22]. In its most basic form, the silicon carrier is a silicon substrate that has fine pitch I/Os and high speed wiring on one side, a typical C4 solder bump on the other side and through-vias that connect the two sides (see Figure 1).…”

Section: Figure 1 Silicon Carrier and Its Electrical Elementsmentioning

confidence: 99%

“…It is clear that unconventional methods that focus beyond the scaling of the CMOS devices have to be employed in order to sustain the performance growth of computer systems. At the system and packaging level, one such method involves use of silicon carrier technology which is capable of providing high I/O density, high speed signaling and efficient power distribution system [7,15]. By supporting signal wiring pitch of less than 2 μm, I/O density pitch of less than 50 μm, chip proximity of less than 100 μm and host of embedded passive devices as well as integration of heterogeneous technologies, the silicon carrier bridges a wide gap that always existed between the chip and the package and in turn, transforms performance limiting packaging bottlenecks into opportunities that system architects and designers can exploit to sustain the historic performance of computer systems.…”

Section: Introductionmentioning

confidence: 99%

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Silicon carrier for computer systems

Patel¹

2006

2006 43rd ACM/IEEE Design Automation Conference

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System-on-Package (SOP) based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. This paper describes the electrical characterization of key technical elements of the silicon carrier and discusses the significance of those elements in enhancing the overall system performance. The paper also discusses some methodologies that may allow silicon carrier technical elements to be easily integrated within existing EDA tools.

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“…Added tools and processes would support silicon through-vias, fine pitch test and assembly capability. This class of new 3D packaging structures and products [1][2][3][4] can offer shorter distance between circuits, integrated function for higher performance and the ability to scale interconnections and bandwidth with new generations of integrated circuits. This paper will discuss the technology challenges and report on research integration demonstrations which are >16x increase over standard chip I/O density, a 20x to 100x increase in wiring density over traditional organic and ceramic packaging, and demonstrated integrated high performance passives.…”

Section: Introductionmentioning

confidence: 99%

System-on-Package (SOP) Technology, Characterization and Applications

Knickerbocker

Andry

Buchwalter

et al.

56th Electronic Components and Technology Conference 2006

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A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers.

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Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

Cited by 32 publications

References 9 publications

Wafer-level 3D integration technology

Wafer-level 3D integration technology

Silicon carrier for computer systems

System-on-Package (SOP) Technology, Characterization and Applications

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