System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

No abstract

No abstract

We propose a new figure of merit to assess the performance of light trapping nanostructures for solar cells, which we call the light trapping efficiency (LTE). The LTE has a target value of unity to represent the performance of an ideal Lambertian scatterer, although this is not an absolute limit but rather a benchmark value. Since the LTE aims to assess the nanostructure itself, it is, in principle, independent of the material, fabrication method or technology used. We use the LTE to compare numerous proposals in the literature and to identify the most promising light trapping strategies. We find that different types of photonic structures allow approaching the Lambertian limit, which shows that the light trapping problem can be approached from multiple directions. The LTE of theoretical structures significantly exceeds that of experimental structures, which highlights the need for theoretical descriptions to be more comprehensive and to take all relevant electro-optic effects into account.