System-on-Package (SOP) Technology, Characterization and Applications

Knickerbocker, John; Andry, Paul; Buchwalter, L.P.; Colgan, E. G.; Cotte, J.; Gan, Hua; Horton, R.; Sri-Jayantha, Sri M.; Magerlein, J. H.; Manzer, Dennis G.; McVicker, Gerard; Patel, C.S.; Polastre, R.; Sprogis, E.; Tsang, C. K.; Webb, Bucknell C.; Wright, S. L.

doi:10.1109/ectc.2006.1645680

Cited by 20 publications

(4 citation statements)

References 13 publications

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“…Use of optical holes for communication between chips to achieve high bandwidth communication has been shown by [13,14]. Use of integrated liquid cooling to address the increasing power consumption in microprocessors has been shown by [15,16,17]. However all these are independent solutions using disparate fabrication processes.…”

Section: I: Introductionmentioning

confidence: 98%

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Parekh

Thadesar

Bakir

2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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Modern high-performance computing systems and data centers are implemented as many-core server systems. Current state of the art data centers have server racks with pluggable boards where each board has many multi-core processors and memory units. These boards are connected via electrical or optical cables. In such systems, communication bandwidth between the high-speed microprocessor cores and the memory is limited. To leverage full performance of these powerful chips, it is required to provide high memory bandwidth as well as effective power delivery and heat removal solutions. To address these challenges in high performance computing systems, we present a 3D packaging solution that includes a novel silicon interposer with electrical, optical, and fluidic (trimodal) interconnects and through-silicon vias (TSVs). The electrical TSVs in the silicon interposer enable power and signal delivery from motherboard to chips stacked on top of the interposer. The optical TSVs in the silicon interposer can provide ultra-high bandwidth communication between chips on different silicon interposers through motherboard level optical links. The fluidic TSVs enable a coolant to be routed from the motherboard to the chips on the silicon interposer. We have fabricated and characterized polymer-clad electrical TSVs (for low stress) with diameter that meets ITRS projections for high-performance computing systems. Using the same polymer used for the cladding of electrical TSVs, we have fabricated and characterized optical TSVs adjacent to electrical TSVs. Spin coating of the photodefinable polymer for electrical and optical TSVs is done in single step. Fabrication of fluidic TSVs can be done using the same cladding as that of the polymer-clad electrical TSVs without electroplating the copper. This leaves behind an empty polymer-clad via which can be used as a fluidic TSV. I: IntroductionThe performance of a processor is commonly measured as the number of instructions it processes per unit time. For high performance and utilization of the processor, the rate at which memory supplies instructions and data to the processor must match with the rate at which the processor is processing them. With the migration towards multi-core and multi-threading, the memory gap problem becomes more acute since now multiple processors on a single chip will increase the memory bandwidth demand. Thus, all the performance benefits of this processor cannot be fully leveraged because memory speeds are much slower compared to the processor speed [1, 2]. Fig. 1 shows scaling in processor frequencies and the memory speed over the past years. To solve this problem, we must improve the memory throughput and reduce the memory latency which includes interconnect delay in addition to memory access delay. This was quantified with analytical simulations to determine the effect of increased memory bandwidth on a processor chip, and we see that performance increase is proportional to the available memory bandwidth. Fig. 2 shows that throughput increases from 96 BIPS (bi...

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Section: I: Introductionmentioning

confidence: 98%

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Parekh

Thadesar

Bakir

2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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“…The performance improvement from complementary metaloxide-semiconductor (CMOS) scaling has been reducing due to a disparity between the rapid rate of CMOS scaling and the slower rate of the development of silicon ancillary technologies [1,2]. To cope with this challenge, 2.5-dimensional (2.5D) and 3-dimensional (3D) interconnection of integrated circuits (ICs) is currently being widely explored to obtain high-bandwidth chip-to-chip communication at lower power consumption [1][2][3][4][5][6]. Silicon interposers with high-density and fine-pitch wiring and through-silicon vias (TSVs) have been shown as a promising substrate technology to support and interconnect multiple single chips as well as 3D chip stacks [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

“…To cope with this challenge, 2.5-dimensional (2.5D) and 3-dimensional (3D) interconnection of integrated circuits (ICs) is currently being widely explored to obtain high-bandwidth chip-to-chip communication at lower power consumption [1][2][3][4][5][6]. Silicon interposers with high-density and fine-pitch wiring and through-silicon vias (TSVs) have been shown as a promising substrate technology to support and interconnect multiple single chips as well as 3D chip stacks [4][5][6]. Figure 1(a) and figure 1(b) show 2.5D and 3D silicon interposers, respectively.…”

Section: Introductionmentioning

confidence: 99%

Novel photodefined polymer-embedded vias for silicon interposers

Thadesar¹,

Bakir²

2013

J. Micromech. Microeng.

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This paper describes the fabrication and characterization of novel photodefined polymer-embedded vias for silicon interposers. The fabricated polymer-embedded vias can help obtain ∼3.8× reduction in via-to-via capacitance as well as a reduction in insertion loss compared to TSVs with a silicon dioxide liner. Polymer-embedded vias 100 μm in diameter, 270 μm tall and at 250 μm pitch were fabricated. Resistance and leakage measurements were performed for the fabricated polymer-embedded vias. The average value of the measured resistance for 20 polymer-embedded vias is 2.54 mΩ and the maximum measured via-to-via leakage current for 10 pairs of polymer-embedded vias is 80.8 pA for an applied voltage of 200 V.

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“…Since actual implementations have been emphasized, die-to-die approaches have taken the lead in development. Technologies in which dies are directly connected to other dies by using vertical interconnects have been proposed and several different processes for making TSVs and low-volume leadfree solder interconnects have been studied [1][2][3][4][5][6]. Each die is aligned and stacked by using high-precision flip chip bonding.…”

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confidence: 99%

Characterization of stacked die using die-to-wafer integration for high yield and throughput

Sakuma

Andry²,

Tsang³

et al. 2008

2008 58th Electronic Components and Technology Conference

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We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-µm thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume leadfree interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mΩ. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications. IntroductionSemiconductor devices have realized improvements in performance with high speed, increased functionality, low power dissipation, and low cost by continuing their remarkable miniaturization and high degree of integration per Moore's Law. However, with further miniaturization to 32 nm and smaller, problems such as increasing costs of capital investment and research and development, as well as technical problems such as increasing transistor leakage current mean that continued miniaturization at historical rates of development is becoming difficult. To address such problems, 3D integrated multiple circuits are considered to be a promising solution. This is because 3D integration technology should make it possible to improve performance by stacking chips with 32 nm features rather than simply shrinking the device dimensions.There are several different approaches for 3D integration, including die-to-die, die-to-wafer, and wafer-to-wafer. Since actual implementations have been emphasized, die-to-die approaches have taken the lead in development. Technologies in which dies are directly connected to other dies by using vertical interconnects have been proposed and several different processes for making TSVs and low-volume leadfree solder interconnects have been studied [1][2][3][4][5][6]. Each die is aligned and stacked by using high-precision flip chip bonding. Die-to-die integration provides higher flexibility and higher yield, since it's possible to sort known good die (KGD) before stacking. However, low fabrication throughput

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System-on-Package (SOP) Technology, Characterization and Applications

Cited by 20 publications

References 13 publications

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Novel photodefined polymer-embedded vias for silicon interposers

Characterization of stacked die using die-to-wafer integration for high yield and throughput

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