Silicon etching yields in F2, Cl2, Br2, and HBr high density plasmas

Vitale, Steven A.; Chae, Heeyeop; Sawin, Herbert H.

doi:10.1116/1.1378077

Cited by 118 publications

(84 citation statements)

References 74 publications

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“…In conventional continuous dry etching trench bottoms are often micro-trenched due to ion scattering from the trench sidewalls which results in faster etching of the side corners. 51 We note that these results have been obtained with non-optimized processing and equipment, so we are confident that further optimization will give further improvements and insights. The process variables are manifold: gas concentration, pressure in the etch and passivation compartments, plasma power, substrate voltage biasing, room temperature processing, 52 plasma source-to-substrate distance, passivation with other spatial ALD oxides like SiO 2 .…”

Section: Microplasma Sourcesmentioning

confidence: 98%

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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Conventional (3D) etching in silicon is often based on the 'Bosch' plasma etch with alternating half-cycles of a directional Sietch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing 'curtains' that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al 2 O 3 , SiO 2 , etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-endof-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Today, the continuous doubling of the transistor count on planar microprocessor and memory chips in a two-year cadence has reached the point where Moore's Law (essentially an economic law) and Dennard's scaling (transistor and pitch dimensions) have approached their limits in 2D-scaling. The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device.1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.Today, at the emergence of the 10-nm technology node and the 50 th anniversary of Moore's Law, 3D device and integration solutions are being rapidly introduced both intra-chip, e.g., Gate-All-Around, 3 vertical NAND, 4 and inter-chip, e.g., 3D Through-Silicon Vias (TSVs). 5History of 3D etching.-Whereas the transistor design has been planar for most of its history, its periphery has been subjected to 3D design early on. One of the earliest 3D concepts has been the basic invention of 3D TSVs, already filed in 1958 by the famous W. Shockley, 6 cf. Fig. 2. Yet, in reality 3D Through-Silicon Via (TSV) technology took decades to accelerate the now rapidly growing stacked-chips and micro-electromechanical systems (MEMS) markets by enabling their interconnection in a 3D-integrated System-in-Package (i.e. the so-called 'More than Moore' domain). Today, the mainstream industrial technology for etching of both TSV and MEMS structures is ion-assisted etching or (Deep) Reactive Ion Etching. This method has become so ...

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Section: Microplasma Sourcesmentioning

confidence: 98%

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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“…41 Moreover, the mass of the ion as well as its incident angle and energy also have an impact on the ion reflection number efficiency and the ion reflection energy efficiency. Ion-assisted chemical etching of silicon depends on the ion incident angle, 42,43 where the etching yield curve is fairly flat and decreases monotonically with off-normal angle. In the model, we are taking into account the fact that the effective ion flux decreases with the incident angle (Lambert's cosine law).…”

Section: B Feature Scale Transport Of Plasma Speciesmentioning

confidence: 98%

“…Consistent with the established literature values, 20,22,43 the ion incident angle dependency of the silicon etch yield Y Si was assumed to have the form f ða in Þ Si ¼ f60 : 85 g and was kept unchanged in the all simulations.…”

Section: -4mentioning

confidence: 99%

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Profile simulation model for sub-50 nm cryogenic etching of silicon using SF6/O2 inductively coupled plasma

Ishchuk

Olynick

Liu

et al. 2015

Journal of Applied Physics

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Cryogenic etching of silicon is a route to high aspect ratio silicon features with high mask selectivity and smooth sidewalls. These benefits have been realized even down to 10 nm half-pitch features. In this work, we develop a semi-empirical simulation model to understand mechanisms responsible for nanoscale profile evolution during plasma etching of silicon in SF6/O2 chemistry at cryogenic temperatures. The model parameters are first calibrated to the etching equipment using features from 500 nm to 2 μm. Using the calibrated model, we show the experimental finding that smaller features need more oxygen to achieve vertical anisotropic profiles. This is a consequence of two related effects: (1) the SiOxFy passivation layer sputtering yield is strongly dependent on the oxygen content at the feature sidewalls and (2) Knudsen transport within small features or higher aspect ratios depletes oxygen faster than fluorine due to the higher sticking coefficient of oxygen. The simulation was applied to 25 nm half-pitch features with excellent results.

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“…[5][6][7][8] As a first step of the etch study for nanometer-size patterns, the effect of the etch gas on the etch characteristics of polysilicon films was examined, and finally etch profiles with nanometer-size patterns were attempted.…”

mentioning

confidence: 99%

Influence of Etch Gas on High Density Plasma Etching of Polysilicon Thin Films with Nanometer-Size Patterns

Song

Chung

2004

Electrochem. Solid-State Lett.

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High density plasma etching of polysilicon thin films with nanometer-size patterns was performed in an inductively coupled plasma. The etch process of polysilicon films with a photoresist mask was characterized using Cl 2 , C 2 F 6 , and HBr gas chemistries in terms of etch rate, etch selectivity, and etch profile. The fast etch rate of polysilicon films was obtained in Cl 2 /Ar gas and the high selectivity of polysilicon to photoresist was found in HBr/Ar gas mixture. The etching of polysilicon films masked by photoresist with nanometer-size patterns was attempted with various etch gases, and an anisotropic etching of 60 nm sized pattern was achieved in HBr/Ar and C 2 F 6 /Ar plasmas.There have been two major technologies in the development of nonvolatile semiconductor memories ͑NVSM͒: the floating-gate structure and the SONOS ͑polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon͒ structure. In the 1970s, the floating-gate structure was a popular choice in semiconductors because equipment was not available to deposit an ultrathin layer of silicon oxide ͑10-30 Å͒ for SONOS structure. However, as the industry gained experience with thin silicon oxide and nitride, the SONOS structure became a viable candidate for scaled NVSM technology. 1,2 The key process technologies in scaled SONOS nonvolatile memory devices are the deposition of ultrathin films of silicon oxide and nitride, and the etching of nanometer size polysilicon gates. The schematics of the SONOS device are shown in Fig. 1. In addition, the formation of a nanometer size channel by an etching process is also a critical technology to be realized. 3,4 Dry etching of polysilicon, as well as silicon oxide thin films, has been widely studied for the fabrication of very large scale and ultralarge scale integrated devices. As the critical dimension of a gate polysilicon reduces to less than nanometer size, the use of a hard mask may be preferred over a photoresist mask in the etching of polysilicon films with nanometer-size patterns. However, the additional processes containing deposition and etching of a hard mask material can act as a disadvantage compared to the use of a photoresist mask.In this study, the possibility of using a photoresist in etching of polysilicon thin films with nanometer-size patterns was explored using Cl 2 , C 2 F 6 , and HBr gases. 5-8 As a first step of the etch study for nanometer-size patterns, the effect of the etch gas on the etch characteristics of polysilicon films was examined, and finally etch profiles with nanometer-size patterns were attempted. ExperimentalPolysilicon thin films were deposited on SiO 2 /Si substrates by a low-pressure chemical vapor deposition ͑LPCVD͒ process. For etch rate and etch selectivity, the deposited polysilicon films were patterned by conventional photolithography and for the nanometer-size patterns on polysilicon films, an E-beam lithography was applied to define the patterns of 50-100 nm lines.The etch equipment used in this study was a high density inductively coupled plasma reactive ...

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Silicon etching yields in F2, Cl2, Br2, and HBr high density plasmas

Cited by 118 publications

References 74 publications

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Profile simulation model for sub-50 nm cryogenic etching of silicon using SF6/O2 inductively coupled plasma

Influence of Etch Gas on High Density Plasma Etching of Polysilicon Thin Films with Nanometer-Size Patterns

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