Silicon-gate CMOS frequency divider for electronic wrist watch

Vittoz, E.A.; Gerber, B.; Leuenberger, F.

doi:10.1109/jssc.1972.1050254

Cited by 38 publications

(10 citation statements)

References 5 publications

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“…All measurements have been made at room temperature. The curves are seen to follow the exponential law up to the limit predicted by (12). The corresponding n UT products reported in Table I are in good agreement with values obtained from (9).…”

Section: Ut+@+vssupporting

confidence: 84%

“…The minimum value of S ensuring weak inversion operation can be calculated from this relation; the factor (n -1 )/ez can be dropped if a rough order of magnitude is all that is needed, so that this upper limit is a direct function of the strong inversion transfer parameter The features of weak inversion operation described by (7) have been verified experiment,ally with a CMOS siIicon-gate technology similar to the one described earlier in [12] . Main parameters are: n-type substrate and p-type wells doping of 2 " 1015 cm-3 and 5 " 1015 cm-3, respectively, after processing, and COX = 340 pF/mm2.…”

Section: Ut+@+vsmentioning

confidence: 82%

“…This type of diode is obtained naturally with silicon-gate technology at every p to n transition of the gate layer. A differential resistance in the range 1-10 Gfl at zero voltage has been measured on 10-Mm width diodes fabricated with the doped-oxide technology [12] . The biasing resistor R, is a single lateral diode.…”

Section: Ut+@+vsmentioning

confidence: 99%

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CMOS analog integrated circuits based on weak inversion operations

Vittoz¹,

Fellrath²

1977

IEEE J. Solid-State Circuits

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701

210

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A simple model describing the dc behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p-and nchannel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (

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Section: Ut+@+vssupporting

confidence: 84%

Section: Ut+@+vsmentioning

confidence: 82%

See 1 more Smart Citation

CMOS analog integrated circuits based on weak inversion operations

Vittoz¹,

Fellrath²

1977

IEEE J. Solid-State Circuits

Self Cite

701

210

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show abstract

“…To minimize power consumption, which often is a concern for clock-based digital circuits, we apply clock gating and use counters based on 1/2 frequency dividers [9] (see Fig. 3 and Fig.…”

Section: mentioning

confidence: 99%

Digital associative memory for word-parrallel Manhattan-distance-based vector quantization

Sasaki

Yasuda

Mattausch

2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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Digital Word-parallel associative-memory architecture capable of Manhattan-distance-based vector quantization is reported, which applies frequency dividers and clock counting to realize nearest Manhattan-distance (MD) search. Experimental verification was done with a 65 nm CMOS design implementing 128 reference vectors, each having 16 components and 16 bit per component. For the fabricated test chips 926 ps minimum search time and 2.13 mW power dissipation are measured at 120MHz and Vdd = 1.2V. At lower supply voltage of Vdd = 0.9V and lower frequency of 20MHz the powerdissipation reduces to 130 W. In comparison to previous digital architecture a factor 100 smaller power delay product (estimated factor 16 when scaled to 65 nm CMOS) is achieved. I.INTRODUCTION Calculating the similarity between collections of objects is needed for different applications such as image/voice pattern recognition, codebook-based data compression or authentication in security system [1,2]. To handle flexible intelligent operations, such as associations in a human brain, it is essential to achieve an efficient VLSI-circuit implementation for this similarity calculation.Solutions realizing efficient word-parallel Hammingdistance (HD) search [3][4][5] are well known. However, most practical applications require the more complicated MD or Euclidean-distance (ED) search. Combined digital-analog methods (MD [6], ED [7]) and a fully-digital method based on a sorting algorithm [MD,8] have been reported, previously. However, these circuits have the problems of low reliability and/or relatively large power consumption. The reported novel digital architecture is capable to implement word-parallel digital MD search with fast search time, low power consumption and faultless precision at the same time. Furthermore, it has the expansion potential to unlimited reference-data capacity.

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“…A large reduction in the 32-kHz frequency is necessary to produce the 15-minute to 4-hour intervals required by this IC. Though chip area was not a problem, minimal r w e r consumption for the frequency reduction is desirab e. After an investigation of alternative methods, a library search yielded a low-power circuit intended for di 'tal watches [4]. This low-power circuit divides the 32-kHz crystayfrequency and roduces a low-frequency clock with a 4-minute period.…”

Section: Proiect Examdlesmentioning

confidence: 99%

An undergraduate full-custom CMOS VLSI design course: CAD tools, fabrication, at MOSIS, and project examples

Sloane

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

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A B S "BuckneN University has developed a senior-design course using a combination of CAD tool famili&dion, and presentations on specific and group topics that are critical to various aspects of IC design Students complete a full-custom CMOS VLSX design and in some cases submit their design for fabrication at MOSIS.Nationally, undergraduate electrical engineering cumcula are under review for their design content. This review is driven both b the Accreditation Board for Engineering Technology (AsEl$ reviews, which are emphatic in their demands for significant design content in the cumcula, and by industry, which has been disappointed with the problem-solving slulls and creativity of current electrical engineering aduates. Design, however, is a difficult concept to define. A Erge portion of the national debate on design in electrical engineerin cumcula focuses on the definition of design. Emerging kom these discussions is a consensus that design components of the cumculum must present open-ended problems which offer alternative solutions or approaches.When faced with typical class sizes, open-ended design problems, with their multiple solutions, present a significant challenge for engineering faculty to evaluate. Students too, are faced with a dilemma. For the student, aside from resortin to construction of the project, which is time consuming and often does not provide substantial insight into the design process, computer-based simulation and analysis tools must be used to assess their design. Unfortunately, in many areas of electrical engineering, either the computer-based analysis and design tools are too rudimentary, computational time excessive, or software costs exceeds the University's means. Fortunately in the area of VLSI, industry and academia have devoted considerable time and expense to the development of accurate, effective, and realistic computer-based design and analysis tools. Bucknell University has developed a senior-design course which uses some of these tools for CMOS VLSI design. Course Overviewcourse for electrical engineering stufents. Students enter t E VLSI course following a two-course electronics se uence; students complete a full-custom CMOS VLSI design by %e end of the semester-long VLSI course.During the initial approximately six weeks of the VLSI course, students are familiarized with the CAD tools through several shorter design projects. T ically, these initial projects are one or two weeks in duration. Yrojects assigned durinbthis familiarization phase have included: optimum sizing of C OS inverters for mimmum ro agation delay; a maximum density, 400fix400p one-bit KO&; a 2-bit parallel multiplier; and an expandable 4-bit arithmetic logic unit. The results from these projects vary widely in quality. For instance, using 3-K technology, within a 4 0 0~ x 400p total area, sizes of the one-bit ROM designs have ranged from 16 bits upwards to 256 bits inclusive of the row and column decoders. Throughout these shorter projects, students gain familiarity with the graphical layout tools, des...

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Silicon-gate CMOS frequency divider for electronic wrist watch

Cited by 38 publications

References 5 publications

CMOS analog integrated circuits based on weak inversion operations

CMOS analog integrated circuits based on weak inversion operations

Digital associative memory for word-parrallel Manhattan-distance-based vector quantization

An undergraduate full-custom CMOS VLSI design course: CAD tools, fabrication, at MOSIS, and project examples

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