Silicon on sapphire CMOS for optoelectronic microsystems

Andreou, Andreas G.; Kalayjian, Z.K.; Apsel, Alyssa; Pouliquen, Philippe O.; Athale, Ravindra A.; Simonis, George J.; Reedy, R.E.

doi:10.1109/7384.963464

Cited by 49 publications

(16 citation statements)

References 5 publications

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“…We designed and fabricated an optical receiver in the 0.25µm ultra-thin silicon-on-sapphire (SOS) technology developed by Peregrine Semiconductor [4]. Similar to other SOI processes, SOS CMOS transistors are fabricated on a 100 nm layer of silicon supported by an insulating sapphire substrate, reducing parasitic capacitance, body effect, and substrate crosstalk between devices.…”

Section: Receiver Architecturementioning

confidence: 99%

A 10 Gb/s optical receiver in 0.25 μm silicon-on-sapphire CMOS

Chen

Pappu

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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An optical receiver designed and fabricated in 0.25µm ultra-thin silicon (UTSi) on sapphire technology is flip-chip integrated with p-i-n photodiodes. The receiver includes a transimpedance amplifier (TIA), limiting amplifiers (LA), and an output buffer. The power consumption of the TIA and limiting amplifiers is 67.3 mW. The receiver is shown operating with a gain of 57 dB at a bit rate of 10 Gb/s. The measured sensitivity is 1.7 dBm for a bit error rate of 10 -9 . This is the first 0.25µm CMOS TIA and LA codesign that operates optically at 10 Gb/s.

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Section: Receiver Architecturementioning

confidence: 99%

A 10 Gb/s optical receiver in 0.25 μm silicon-on-sapphire CMOS

Chen

Pappu

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The smart pixel chips combine Ultra-Thin Silicon (UTSi) ASICs with VCSEL and detector arrays and micro-lens collimating elements. The inherent transparency of the sapphire substrate of the ASIC obviates the need for any substrate removal of the VCSEL and detector arrays [37]. The emitted light passes through the sapphire substrate and the back surface of the sapphire provides a convenient location to implement beam-conditioning micro-optics.…”

Section: D Free-space Optics Summarymentioning

confidence: 99%

RATS: Reactive Architectures

Christensen¹,

Kiamelev²,

Haney³

et al. 2004

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)This project had two goals: To build an emulation prototype board for a tiled architecture and to demonstrate the utility of a global inter-chip free-space photonic interconnection fabric for polymorphous computer architectures (PCA). The free-space optics part of the project focused on two critical issues to validate the use of ultra-high-capacity global freespace interconnection fabrics for polymorphous computing architectures. These issues fell into the categories of interface issues and internal switch issues. The VCSEL-based free-space optical system was shown to be tolerant of misalignments, although electrical packaging problems prevented a full-performance demonstration. The optical links for the free-space system were demonstrated at 2.5 Gbps each with an inter-chip distance of about 10 cm. The project successfully demonstrated an optical inter-board fiber-based interconnect and intra-board free-space interconnect. The project also developed a prototype board that was demonstrated with an emulator of a tiled architecture.

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“…The mechanical polishing resulted in an optically clear die on both side. Alternatively index matching fluid can be employed to fill in the asperities of the backside [2]. The effectiveness of the mechanical polishing is evident in figure 3.…”

Section: Resultsmentioning

confidence: 97%

“…In the next version of the chip, the wired-or will be replaced with a tree based fully CMOS design, thus reducing dramatically the power dissipation. The circuit design both for the pixel and periphery employs the available zero threshold transistors [2] to reduce the complexity, minimizing the number of transistors and wires necessary for bias circuits. Both analog and digital power consumption measurements were conducted using a supply voltage of 3.3V and with an output event rate of 0.48M events/s.…”

Section: Resultsmentioning

confidence: 99%

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A 16 × 16 pixel silicon on sapphire CMOS photosensor array with a digital interface for adaptive wavefront correction

Culurciello

Andreou

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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We report on a 16 × 16 pixel CMOS photosensor array fabricated in silicon on sapphire CMOS technology. The transparency of the substrate allows imaging from both the back and front side and opens new applications for CMOS active pixel sensor arrays. A digital asynchronous interface is employed to minimize the design complexity and the the power consumption. The analog pixel value is encoded as a pulse density stream of address events. The multiple threshold MOS transistors available in this technology enable circuit optimizations for low power and low voltage operation. We characterize the pixel sensitivity and show experimental data from both back and front side imaging.

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Silicon on sapphire CMOS for optoelectronic microsystems

Cited by 49 publications

References 5 publications

A 10 Gb/s optical receiver in 0.25 μm silicon-on-sapphire CMOS

A 10 Gb/s optical receiver in 0.25 μm silicon-on-sapphire CMOS

RATS: Reactive Architectures

A 16 × 16 pixel silicon on sapphire CMOS photosensor array with a digital interface for adaptive wavefront correction

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