Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration

Kim, Jin-Woo; Chekuri, Venkata Chaitanya Krishna; Rahman, Nael Mizanur; Dolatsara, Majid Ahadi; Torun, Hakki Mert; Swaminathan, Madhavan; Mukhopadhyay, Saibal; Lim, Sung Kyu

doi:10.1109/iccd50377.2020.00030

Cited by 14 publications

(1 citation statement)

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“…This approach significantly reduces the design cycle, complexity and cost. It enables the heterogeneity of blocks in multiple technologies and permits the reuse of off-the-shelf intellectual properties (IPs) [6,7]. Instead of redesigning the entire system, SoC designers can replace only the necessary chiplets.…”

Section: Introductionmentioning

confidence: 99%

New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

et al. 2022

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A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

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Section: Introductionmentioning

confidence: 99%