Silicon Wafer Thinning to Reveal Cu TSV

Mauer, Laura; Taddei, John; Youssef, Ramey

doi:10.4071/2012dpc-wp11

Cited by 4 publications

(1 citation statement)

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“…Dry etch processes usually require expensive equipment and etching gases. On the other hand, wet chemicals such as KOH and TMAH have been used as cost-effective wet etch alternatives for plasma etching to reveal the TSV [1,2]. The issue with the KOH process is that KOH adds metal ion (K + ) contamination on wafer surfaces.…”

Section: Introductionmentioning

confidence: 99%

Wet silicon etch process for TSV reveal

Mauer¹,

Taddei²,

Youssef³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper presents a wet process as a simple and costeffective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool. The new selective etch chemistry improves the etch rate by 50% or more over traditional Si etchants currently used in the industry, such as tetramethylammonium hydroxide (TMAH). This new etch chemistry also has high silicon-etch selectivity over the oxide liner and Cu, with etch rate (ER) ratios greater than 10,000 and 1000, respectively. TMAH is not a component in the chosen chemistry because of safety concerns specifically related to TMAH toxicity.Variations in the depth of the Si overburden occur due to non-uniformities in post-grind thickness, via depth, and bonding. To compensate, an algorithm is used to control etch profiles. Integration of wafer thickness measurements before and after etching-within the single-wafer equipment-provides the high-accuracy process control needed for high-volume manufacturing. Improvement in surface roughness and etch uniformity are achieved with this wet process through the combination of chemistry performance and process optimization. IntroductionMobility and performance demands from semiconductor end users have continually driven the semiconductor device geometry to smaller dimensions. The same pressure has also resulted in many innovations from the semiconductor packaging industry. One of these innovations is the Through Silicon Via (TSV) 3D packaging technology. Through Silicon Via has become the key enabling technology in 3D packaging by reducing interconnect length to increase device speed, and by increasing interconnect density to reduce the package form factor. There are three different integration schemes with the TSV process: via-first, via-middle, and via-last. The via-first process forms the TSV in the substrate silicon before the front-end process. The via-middle process forms the TSV at the front end or interconnect steps with the regular wafer process flow. The via-last process makes the TSV from the backside of the wafer after completing the BEOL processing. In via-first and via-middle TSV integration flows, Si wafers must be thinned from the backside to reveal the Cu vias for the wafer to make contact with another wafer or chips. Typically, this thinning is accomplished by grinding the back

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Section: Introductionmentioning

confidence: 99%