Thin wafers have become a basic need for a wide variety of new microelectronic products. Thinner die are being required to fit into thinner packages. Wafers that have been thinned using a final wet etch process on the backside have less stress compared with standard mechanical backgrinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids along with the addition of chemicals to adjust for viscosity and surface wettability for single wafer spin processing. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control techniques for maintaining a consistent etch rate as a function of time and wafers processed. The models allow for either the time to be extended, chemicals to be replenished or a combination of these. Results will be presented including the cost of ownership for each scenario.

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This paper presents a wet process as a simple and costeffective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool. The new selective etch chemistry improves the etch rate by 50% or more over traditional Si etchants currently used in the industry, such as tetramethylammonium hydroxide (TMAH). This new etch chemistry also has high silicon-etch selectivity over the oxide liner and Cu, with etch rate (ER) ratios greater than 10,000 and 1000, respectively. TMAH is not a component in the chosen chemistry because of safety concerns specifically related to TMAH toxicity.Variations in the depth of the Si overburden occur due to non-uniformities in post-grind thickness, via depth, and bonding. To compensate, an algorithm is used to control etch profiles. Integration of wafer thickness measurements before and after etching-within the single-wafer equipment-provides the high-accuracy process control needed for high-volume manufacturing. Improvement in surface roughness and etch uniformity are achieved with this wet process through the combination of chemistry performance and process optimization. IntroductionMobility and performance demands from semiconductor end users have continually driven the semiconductor device geometry to smaller dimensions. The same pressure has also resulted in many innovations from the semiconductor packaging industry. One of these innovations is the Through Silicon Via (TSV) 3D packaging technology. Through Silicon Via has become the key enabling technology in 3D packaging by reducing interconnect length to increase device speed, and by increasing interconnect density to reduce the package form factor. There are three different integration schemes with the TSV process: via-first, via-middle, and via-last. The via-first process forms the TSV in the substrate silicon before the front-end process. The via-middle process forms the TSV at the front end or interconnect steps with the regular wafer process flow. The via-last process makes the TSV from the backside of the wafer after completing the BEOL processing. In via-first and via-middle TSV integration flows, Si wafers must be thinned from the backside to reveal the Cu vias for the wafer to make contact with another wafer or chips. Typically, this thinning is accomplished by grinding the back

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3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.