This paper presents a wet process as a simple and costeffective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool. The new selective etch chemistry improves the etch rate by 50% or more over traditional Si etchants currently used in the industry, such as tetramethylammonium hydroxide (TMAH). This new etch chemistry also has high silicon-etch selectivity over the oxide liner and Cu, with etch rate (ER) ratios greater than 10,000 and 1000, respectively. TMAH is not a component in the chosen chemistry because of safety concerns specifically related to TMAH toxicity.Variations in the depth of the Si overburden occur due to non-uniformities in post-grind thickness, via depth, and bonding. To compensate, an algorithm is used to control etch profiles. Integration of wafer thickness measurements before and after etching-within the single-wafer equipment-provides the high-accuracy process control needed for high-volume manufacturing. Improvement in surface roughness and etch uniformity are achieved with this wet process through the combination of chemistry performance and process optimization. IntroductionMobility and performance demands from semiconductor end users have continually driven the semiconductor device geometry to smaller dimensions. The same pressure has also resulted in many innovations from the semiconductor packaging industry. One of these innovations is the Through Silicon Via (TSV) 3D packaging technology. Through Silicon Via has become the key enabling technology in 3D packaging by reducing interconnect length to increase device speed, and by increasing interconnect density to reduce the package form factor. There are three different integration schemes with the TSV process: via-first, via-middle, and via-last. The via-first process forms the TSV in the substrate silicon before the front-end process. The via-middle process forms the TSV at the front end or interconnect steps with the regular wafer process flow. The via-last process makes the TSV from the backside of the wafer after completing the BEOL processing. In via-first and via-middle TSV integration flows, Si wafers must be thinned from the backside to reveal the Cu vias for the wafer to make contact with another wafer or chips. Typically, this thinning is accomplished by grinding the back

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3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and 3-D platforms allows a decrease in interconnection path length, which results in improved device performance and reliability in a small form factor. Mainly due to its high silicon etch rate and selectivity to mask materials, the Bosch process is often used in the TSV fabrication. In this process, the silicon via is created by the deep reactive ion etching (DRIE). DRIE is comprised of repeating a combination of steps: an etch step and a passivation step. The passivation created in the DRIE process results in a fluoropolymer residue remaining on the wafer at the end of the process. The residue must be removed to enable deposition of a defect-free barrier, which enables a defect-free seed layer and void-free plating into the via. There are numerous technical papers and presentations on the etching and filling of these vias but the process for cleaning remains under addressed. Initially, standard processes used after RIE and consisting of an ashing process to remove any remaining photoresist, followed by immersion in a solution-based post etch residue remover were adopted for post-TSV cleans. However, the fluoropolymer does not have the same chemical characteristics as typical post-RIE etch residues and the major challenge has been the difficulty to completely remove it, especially on the via sidewall, using traditional post etches residue removers. Therefore, new formulated cleaning solutions and processes are actively sought for the removal of post etch residue for TSVs. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using a proprietary environmentally friendly chemistry, coupled with a megasonic final rinse provides a unique solution for both polymer residue and photoresist removals on high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.