Simple, fast, 2.5-V CMOS logic with 0.25-μm channel lengths and damascene interconnect

Koburger, Charles W.; Adkisson, J.; Clark, William F.; Davari, B.; Geissler, S.; Givens, J.H.; Hansen, H.; Holmes, Steven J.; Lee, H.K.; Lee, J.; Luce, S.; Martin, D.; Mittl, S.; Nakos, J.; Stiffler, S. R.

doi:10.1109/vlsit.1994.324443

Cited by 9 publications

(4 citation statements)

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“…It is found that increasing As or P dose in the hybrid junction decreases inverter propagation delay. With increasing from 2.9 to 3.1 V, inverter gate delay reduced from 32 to 31 ps for of 0.19 m These results are significantly better than the results reported using As-only junctions (48 ps at 0.20-m channel length [3], and 38 ps at 0.18-m channel length [2]). …”

Section: Device Resultsmentioning

confidence: 55%

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A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Nayak

Hao

Umali

et al. 1997

IEEE Electron Device Lett.

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A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L e of 0.19 m, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/m at 2.9 V have been achieved.

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Section: Device Resultsmentioning

confidence: 55%

“…Using As-only n , high-performance CMOS logic technology operating at 2.5 V has been reported [1]- [3]. Due to the sharp As junction, the power supply voltage must be reduced below 2.5 V in order to maintain sufficient hot carrier reliability margin.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Nayak

Hao

Umali

et al. 1997

IEEE Electron Device Lett.

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“…IBM invested heavily in this time to introduce improved RTP equipment and upgrade existing equipment to capture these advantages. With this upgraded fleet of equipment we were able to successfully implement RTP on the most sensitive and device critical processes in the CMOS process flow [32]. After this success, almost any process could be considered for migration to RTP, the selection criteria became predominately a function of cost, qualification time, and resource requirements [33].…”

Section: Expanding Rolementioning

confidence: 99%

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

Nakos

Shepard

2008

MSF

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The role of single wafer Rapid Thermal Processing (RTP) in semiconductor manufacturing has been steadily expanding over the last 2 decades. There are several reasons for the successful adaptation of this technology. These include more critical requirements by advanced semiconductor technologies with respect to thermal exposure and control, as well as tremendous improvements by the RTP equipment community in resolving some fundamental limitations of the tooling, historically restricting wide spread implementation. From rather humble beginnings, RTP technology has now established itself as indispensable to the production of advanced semiconductor products. We review the history and implementation of RTP technology in semiconductor processing technology at International Business Machines Corporation (IBM) from the late 1980s to recent time.

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“…In this table the operating frequency, chip size, power-supply voltage, and power dissipation of an existing high performance RISC processor and projections into more advanced scaled CMOS are presented. The 66 MHz chip with 120 mm2 die size at 0.65 pm lithography, consumes about 7 W. The 100 MHz chip, consuming only 3.4 W, is fabricated in selectively scaled 0.25 pm CMOS technology [27] with 74 mm2 die size, operating at 2.5 V with 3.3 V or 5 V UO. It is estimated that by operating this chip at 1.5 V the power dissipation will be reduced to 0.8 W at 66 MHz.…”

Section: Cmos Scaling Guideline For the Next Ten Yearsmentioning

confidence: 99%

CMOS scaling for high performance and low power-the next ten years

1995

Self Cite

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A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described, one optimized for highest speed and the other trading offspeed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 pm channel length at 2.5 V down to sub-0.1 p m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the powersupply voltage will lead to a substantial rise in standby power compared to active power, and some tradeoffs of performance andor changes in design methods must be made. Key technology elements and their impact on scaling are discussed.It is shown that a speed improvement of about 7x and over two orders of magnitude improvement in power-delay product (mW/MlPS) are expected by scaling of bulk CMOS down to the sub-0.1 pm regime as compared with today's high performance 0.6 p m devices at 5 V. However, the power density rises by a factor of 4 X for the high-speed scenario. The status of the siliconon-insulator (Sol) approach to scaled CMOS is also reviewed, showing the potential for about 3x savings in power compared to the bulk case at the same speed.

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Simple, fast, 2.5-V CMOS logic with 0.25-μm channel lengths and damascene interconnect

Cited by 9 publications

References 1 publication

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

CMOS scaling for high performance and low power-the next ten years

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