Simplified Model Analysis of Self-Excited Oscillation and Its Suppression in a High-Voltage Common Package for Si-IGBT and SiC-MOS

Saito, Kazutoshi; Miyoshi, T.; Kawase, Daisuke; Hayakawa, Seiichi; Masuda, Takatsugu; Sasajima, Yasushi

doi:10.1109/ted.2018.2796314

Cited by 29 publications

(8 citation statements)

References 18 publications

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“…To analyze transfer function H(s), its parameters should be obtained. Following the approach proposed in [19], [21]- [23], [26], [28], the nonlinear behaviour of resonant circuit is neglected. The parameters can thereby be extracted at their dc operating point.…”

Section: Analytical Modeling Of the Test Circuit Utilizing Power Loop...mentioning

confidence: 99%

Ferrite Beads Design to Improve Turn-Off Characteristics of Cascode GaN HEMTs: An Optimum Design Method

Xue

Iannuzzo

2023

IEEE J. Emerg. Sel. Topics Power Electron.

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In this paper, an optimum ferrite beads design method is proposed to suppress the self-sustained turn-off oscillation of cascode gallium nitride high-electron-mobility transistors (GaN HEMTs). At first, the impacts of gate loop beads and power loop beads on the turn-off oscillation of cascode GaN HEMTs are analyzed. The analysis reveals the weak damping effect of gate loop beads on the turn-off oscillation. Next, an analytical method is proposed to design the power loop beads that can achieve maximum effective damping on the turn-off oscillation.The power loop beads introduce extra stray inductance in the power loop, which can induce high voltage overshoot. To tackle the problem, an optimum design method is proposed so that the power loop beads can suppress the oscillation while mitigating the voltage overshoot. The accuracy of the proposed model is validated by the experimental data in the end.

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Section: Analytical Modeling Of the Test Circuit Utilizing Power Loop...mentioning

confidence: 99%

Ferrite Beads Design to Improve Turn-Off Characteristics of Cascode GaN HEMTs: An Optimum Design Method

Xue

Iannuzzo

2023

IEEE J. Emerg. Sel. Topics Power Electron.

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“…However, it not only consumes extra area in package, but also introduces parasitic inductance, which limits switching frequency and reduces the power density in power converter/inverter apparatus. [1] Integrating SBDs can address these problems, [2,3] which will degrade blocking characteristic and thermal stability nevertheless. The parasitic PN body diode in SiC MOS can realize reverse conduction function.…”

Section: Introductionmentioning

confidence: 99%

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

Wang¹,

Jiang²,

Luo³

et al. 2023

Chinese Phys. B

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A novel SiC double-trench MOSFET with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source Trench (MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage (V F) and suppresses the bipolar degradation phenomena. The V F of 1.70V (@ I ds = -100 A/cm2) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET (DT MOS). Meanwhile, the reverse recovery charge Q rr of the MT MOS is 58.7% lower than that of the DT MOS at I load = 700A/cm2, and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches, the MT MOS preserves same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on BV and R ON,sp than the trench gate MOSFET with planar integrated SBD (ST MOS).

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“…Because the timing of gate voltage spike corresponds to the change of digital control vectors, which means I g is pulled up or pulled down [1], [7], [8], [9], [10], it can be expected that V g_spike results from the coupling of dI g /dt and stray gate inductance L g inside IGBT power modules. In previous works, although the relation between current charge and stray inductance of the main circuit loop inside power modules at conventional gate driving for suppressing the collector voltage surge was reported [18], [19], gate inductance design of IGBT module for DGD have not been investigated.…”

Section: Introductionmentioning

confidence: 99%

IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control

et al. 2023

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This paper clarifies the effect of gate inductance L g inside IGBT modules on gate voltage spikes when a digital gate driver is employed. Three IGBT modules with different L g were fabricated to implement double pulse tests by conventional gate driving and digital control gate driving with three-step vectors. It was found that the tradeoff between switching loss and voltage/current overshoots can be improved by digital control, but a large gate voltage spike was generated when gate-driving vectors were changed. And the spike voltage V g_spike was positively correlated to the L g . Although the V g_spike can also be suppressed by decreasing the difference of gate driving vectors between the first and the second steps, the improvement of the tradeoff is weakened. Therefore, it is required that the L g inside the IGBT modules should be reduced to suppress the V g_spike while improving the tradeoff by the digital gate driver at the same time. Furthermore, by analyzing the oscillation of the V g_spike , it indicates that there should be some other stray elements, which couple L g and the stray capacitance inside IGBT chips, affecting the V g_spike .INDEX TERMS IGBT power module, gate inductance, digital gate driver, switching loss, current overshoot, voltage overshoot, gate voltage spike.

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Simplified Model Analysis of Self-Excited Oscillation and Its Suppression in a High-Voltage Common Package for Si-IGBT and SiC-MOS

Cited by 29 publications

References 18 publications

Ferrite Beads Design to Improve Turn-Off Characteristics of Cascode GaN HEMTs: An Optimum Design Method

Ferrite Beads Design to Improve Turn-Off Characteristics of Cascode GaN HEMTs: An Optimum Design Method

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control

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