Simulating the impact of pattern-dependent poly-CD variation on circuit performance

Stine, B.E.; Boning, Duane S.; Chung, J.E.; Ciplickas, Dennis; Kibarian, J.K.

doi:10.1109/66.728551

Cited by 16 publications

(2 citation statements)

References 17 publications

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“…[6,7]). Although some of the variation can be corrected using optical proximity correction (OPC), significant discrepancies still eKist between the measurements and models even after correction.…”

Section: A Clock Treementioning

confidence: 97%

Technology scaling impact of variation on clock skew and interconnect delay

Mehrotra

Boning

2001

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

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Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180nm to 50nm. For the case considered, we show that (1) clock skew increases fiom about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations.

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Section: A Clock Treementioning

confidence: 97%

Technology scaling impact of variation on clock skew and interconnect delay

Mehrotra

Boning

2001

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

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“…Significant research efforts have focused on understanding the causes and effects of spatial variations [24,23,13,1,10,15,26]. The variations are caused by either global effects [24] * Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation. This work was carried out at the NSF's State/Industry/University Cooperative Research Centers' (NSF-S/IUCRC) Center for Low Power Electronics (CLPE).…”

Section: Introductionmentioning

confidence: 99%

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Bhardwaj

Vrudhula

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N | 2 ) and that of evaluating the delay constraints is O(|N | + |E|) for a circuit with |N | gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

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Increasing Circuit Performance through Statistical Design Techniques

Orshansky

Closing the Gap Between ASIC &Amp; Custom

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Simulating the impact of pattern-dependent poly-CD variation on circuit performance

Cited by 16 publications

References 17 publications

Technology scaling impact of variation on clock skew and interconnect delay

Technology scaling impact of variation on clock skew and interconnect delay

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Increasing Circuit Performance through Statistical Design Techniques

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