Technology scaling impact of variation on clock skew and interconnect delay

Abstract

Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180nm to 50nm. For the case considered, we show that (1) clock skew increases fiom about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations.

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

“…5. The signal delay can be approximately calculated by Elmore delay model [5], which is a widely used delay model, as shown in (1).…”

“…Conventionally, there have been some researches which address the impact of process variations on clock skew. Reference [1] investigates the impact of process variations on clock skew and shows that the ratio of clock skew to clock period increases as the LSI process technology scaling. Reference [2] proposed a method for constructing nontree clock networks for reducing clock skew fluctuations caused by wire width variations.…”

Optimal Useful Clock Skew Scheduling In the Presence of Variations Using Robust ILP Formulations

“…Although useful skew enables systems to operate at higher clock frequencies, more and more signal paths get pushed towards the edge of satisfying timing requirements. As the amount of uncertainty increases with scaling [15], [13], [9], the probability of failure for a design with useful skew increases. The random process and environmental variations that dominate the behavior of * Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Characterisation of FPGA Clock Variability

“…These include work employing Monte Carlo simulations [3,10] as well as approaches based on canonical or numerical analysis of the classical H-tree clock structure [1,2]. To date, there is no published report on the measurement or analysis of clock tree variability in FPGAs.…”