Simulation and experimental characterization of reservoir and via layout effects on electromigration lifetime

Analysis of the reservoir effect on electromigration reliability

“…Many experimental works [1][2][3][4][5] for verifying the reservoir effect have been published and all of them demonstrate that electromigration lifetime is dominated by the reservoir area and the number of contacts/vias. Some numerical works [6][7][8][9] for analysis of the reservoir effect by finite element method are also reported. The median-time-to-failure (MTF) calculated by relative resistance change is compared with experimentally measured MTF results of various test structures to show the relation between reservoirs/vias layout and electromigration lifetime.…”

Effect of current crowding on electromigration lifetime investigated by simulation and experiment

“…1b, N = 1 Â 4 called row and N = 2 Â 2 called square) were carried out with at two different stress current densities of J = 12.05 and 19.66 mA/lm 2 at a stress temperature of T = 225 °C. The relative resistance change (RRC) has been calculated as presented in [9] and shown in Fig. 3.…”

Emerging yield and reliability challenges in nanometer CMOS technologies

“…Because of the fixed thickness of the interconnect in a standard CMOS process, wires must be widened to reduce the degradation. Special layout techniques such as Slotted Wires [25] and good orientation of vias (Reservoir effect) [30] can also be used to avoid EM problems. Some of these techniques can be applied automatically by the use of an EM-aware design flow [25].…”