Simulation and Experiments of Stress Migration for Cu/low-k BEoL

The stress-inducing effects of neighboring metal interconnect features were studied using novel stressmigration test structures with various layouts of perpendicular neighboring combs. The structures with narrow widths showed no change in stressmigration performance, with or without near-neighbor structures. However, structures built with wider lines showed up to 3X worse stressmigration performance when perpendicular combs were present nearby, essentially independent of the spacing to the combs. Thus, near neighbor metal features were shown to be capable of degrading SM performance in some lines. Keywords-stress; voiding; test structure I. ABSTRACTPublications in MEMS technologies report the use of thermal expansion to cause deflection of a free-floating needle [1][2][3][4][5][6][7]. This can be used to measure the stress applied by neighboring (and connected) features. Free-floating shapes don't exist in a typical CMOS technology but the stress applied by neighboring structures is still present. As stress can modulate the reliability of the interconnects [8-12], understanding the impact of any neighboring features is important.This study used a novel test structure to apply stress to a via chain using comb features that had no electrical connection. Measurements of resistance shift due to stress-induced voiding (SIV), also known as stressmigration (SM), were used as a metric for that stress. Neighboring combs with various layouts were investigated, in order to test the hypothesis that perpendicular "aggressor" metal lines would apply stress to the device under test (DUT), resulting in worse SM performance. Furthermore, the effect should decrease with the distance between the aggressor lines and the DUT. SM is generally determined by measuring the initial resistance of a DUT, baking it at an elevated temperature (e.g., 150-225°C) for a long time (e.g., 1000 hrs) with no current flow, and then measuring its resistance again. The shift in resistance is its SM performance. In such a high-temperature environment, vacancies in metal interconnects can migrate and accumulate at the regions of stress discontinuities (e.g., vias), resulting in higher resistance. Therefore, a lower resistance shift after baking indicates better SM robustness in the sample.

show abstract

“…SM was a strong function of the DUT width, a trend consistent with what has been reported [11][12][13][14][15]. Fig.…”

Section: A Narrow-base Combssupporting

confidence: 87%

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

Smith

Shroff

2014

2014 International Conference on Microelectronic Test Structures (ICMTS)

View full text Add to dashboard Cite

show abstract

“…The most important reliability concerns for interconnects are electromigration [1][2][3][4], stress-induced voiding [5][6][7], and timedependent dielectric breakdown (TDDB) of the backend dielectric.…”

Section: Backend Dielectric Breakdown Models and Microprocessor Lifetmentioning

confidence: 99%

Backend dielectric reliability simulator for microprocessor system

Chen

Ahmed

Kim

et al. 2012

Microelectronics Reliability

View full text Add to dashboard Cite

“…The plastic strain contours shown in Fig. 22 may also explain other experimentally observed voiding phenomena including void formation at the via bottom [234,315], near the trench shoulder area [321], and along the top interface of the lower-level Cu [234,310]. Within the simple continuum framework, the analysis of constrained deformation is seen to yield meaningful and relevant information regarding the structural integrity of Cu interconnects.…”

Section: Multilevel Interconnectsmentioning

confidence: 64%

“…The via and its vicinity are frequently susceptible to voiding failure. Numerical deformation analyses on Al and Cu interconnects focusing on the via region have been carried out [304][305][306][307][308][309][310][311][312][313][314][315][316]. Here we present a recent simulation, with attention directed to the effects of dielectric materials on Cu deformation.…”

Section: Multilevel Interconnectsmentioning

confidence: 99%

Externally constrained plastic flow in miniaturized metallic structures: A continuum-based approach to thin films, lines, and joints

Shen

2008

Progress in Materials Science

View full text Add to dashboard Cite

Simulation and Experiments of Stress Migration for Cu/low-k BEoL

Cited by 36 publications

References 6 publications

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

Backend dielectric reliability simulator for microprocessor system

Externally constrained plastic flow in miniaturized metallic structures: A continuum-based approach to thin films, lines, and joints

Contact Info

Product

Resources

About